Merge ktlim@zamp:./local/clean/o3-merge/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
Hand merge.
--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
This commit is contained in:
Kevin Lim
@@ -230,7 +230,7 @@ InstructionQueue<Impl>::regStats()
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.name(name() + ".iqSquashedNonSpecRemoved")
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.desc("Number of squashed non-spec instructions that were removed")
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.prereq(iqSquashedNonSpecRemoved);
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/*
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queueResDist
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.init(Num_OpClasses, 0, 99, 2)
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.name(name() + ".IQ:residence:")
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@@ -240,6 +240,7 @@ InstructionQueue<Impl>::regStats()
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for (int i = 0; i < Num_OpClasses; ++i) {
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queueResDist.subname(i, opClassStrings[i]);
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}
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*/
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numIssuedDist
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.init(0,totalWidth,1)
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.name(name() + ".ISSUE:issued_per_cycle")
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@@ -268,7 +269,7 @@ InstructionQueue<Impl>::regStats()
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//
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// How long did instructions for a particular FU type wait prior to issue
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//
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/*
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issueDelayDist
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.init(Num_OpClasses,0,99,2)
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.name(name() + ".ISSUE:")
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@@ -281,7 +282,7 @@ InstructionQueue<Impl>::regStats()
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subname << opClassStrings[i] << "_delay";
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issueDelayDist.subname(i, subname.str());
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}
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*/
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issueRate
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.name(name() + ".ISSUE:rate")
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.desc("Inst issue rate")
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@@ -385,8 +386,16 @@ template <class Impl>
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void
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InstructionQueue<Impl>::switchOut()
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{
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/*
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if (!instList[0].empty() || (numEntries != freeEntries) ||
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!readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
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dumpInsts();
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// assert(0);
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}
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*/
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resetState();
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dependGraph.reset();
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instsToExecute.clear();
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switchedOut = true;
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for (int i = 0; i < numThreads; ++i) {
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memDepUnit[i].switchOut();
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@@ -642,9 +651,12 @@ template <class Impl>
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void
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InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
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{
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DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
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// The CPU could have been sleeping until this op completed (*extremely*
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// long latency op). Wake it if it was. This may be overkill.
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if (isSwitchedOut()) {
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DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
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inst->seqNum);
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return;
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}
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@@ -1036,6 +1048,10 @@ InstructionQueue<Impl>::doSquash(unsigned tid)
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(squashed_inst->isMemRef() &&
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!squashed_inst->memOpDone)) {
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DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
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"squashed.\n",
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tid, squashed_inst->seqNum, squashed_inst->readPC());
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// Remove the instruction from the dependency list.
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if (!squashed_inst->isNonSpeculative() &&
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!squashed_inst->isStoreConditional() &&
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@@ -1066,7 +1082,7 @@ InstructionQueue<Impl>::doSquash(unsigned tid)
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++iqSquashedOperandsExamined;
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}
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} else {
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} else if (!squashed_inst->isStoreConditional() || !squashed_inst->isCompleted()) {
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NonSpecMapIt ns_inst_it =
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nonSpecInsts.find(squashed_inst->seqNum);
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assert(ns_inst_it != nonSpecInsts.end());
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@@ -1093,10 +1109,6 @@ InstructionQueue<Impl>::doSquash(unsigned tid)
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count[squashed_inst->threadNumber]--;
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++freeEntries;
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DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
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"squashed.\n",
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tid, squashed_inst->seqNum, squashed_inst->readPC());
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}
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instList[tid].erase(squash_it--);
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