regess: protocol regression tester updates
This commit is contained in:
@@ -1,13 +1,22 @@
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[root]
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type=Root
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children=system
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dummy=0
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time_sync_enable=false
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time_sync_period=100000000
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time_sync_spin_threshold=100000
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[system]
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type=System
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children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
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mem_mode=timing
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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[system.dir_cntrl0]
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type=Directory_Controller
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@@ -130,6 +139,7 @@ tracer=system.ruby.tracer
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[system.ruby.cpu_ruby_ports]
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type=RubySequencer
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access_phys_mem=true
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dcache=system.l1_cntrl0.L1DcacheMemory
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deadlock_threshold=500000
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icache=system.l1_cntrl0.L1IcacheMemory
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@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Jan/13/2011 22:36:32
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Real time: Feb/08/2011 17:31:55
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 2
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Elapsed_time_in_minutes: 0.0333333
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Elapsed_time_in_hours: 0.000555556
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Elapsed_time_in_days: 2.31481e-05
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Elapsed_time_in_seconds: 0
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Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Virtual_time_in_seconds: 2.32
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Virtual_time_in_minutes: 0.0386667
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Virtual_time_in_hours: 0.000644444
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Virtual_time_in_days: 2.68519e-05
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Virtual_time_in_seconds: 0.79
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Virtual_time_in_minutes: 0.0131667
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Virtual_time_in_hours: 0.000219444
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Virtual_time_in_days: 9.14352e-06
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Ruby_current_time: 352261
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Ruby_start_time: 0
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Ruby_cycles: 352261
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mbytes_resident: 19.4023
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mbytes_total: 155.219
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resident_ratio: 0.12505
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mbytes_resident: 33.6719
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mbytes_total: 208.004
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resident_ratio: 0.161956
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ruby_cycles_executed: [ 352262 ]
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@@ -117,9 +117,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4457 average: 0 | standa
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Resource Usage
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--------------
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page_size: 4096
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user_time: 2
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user_time: 0
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system_time: 0
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page_reclaims: 5638
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page_reclaims: 9831
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page_faults: 0
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swaps: 0
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block_inputs: 0
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@@ -5,10 +5,10 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Jan 13 2011 22:36:25
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M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
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M5 started Jan 13 2011 22:36:30
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M5 executing on scamorza.cs.wisc.edu
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M5 compiled Feb 8 2011 17:31:51
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M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
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M5 started Feb 8 2011 17:31:55
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M5 executing on SC2B0617
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command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
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Global frequency set at 1000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@@ -1,8 +1,8 @@
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---------- Begin Simulation Statistics ----------
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host_mem_usage 158948 # Number of bytes of host memory used
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host_seconds 1.84 # Real time elapsed on the host
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host_tick_rate 191255 # Simulator tick rate (ticks/s)
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host_mem_usage 213000 # Number of bytes of host memory used
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host_seconds 0.47 # Real time elapsed on the host
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host_tick_rate 753338 # Simulator tick rate (ticks/s)
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sim_freq 1000000000 # Frequency of simulated ticks
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sim_seconds 0.000352 # Number of seconds simulated
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sim_ticks 352261 # Number of ticks simulated
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@@ -1,13 +1,22 @@
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[root]
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type=Root
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children=system
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dummy=0
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time_sync_enable=false
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time_sync_period=100000000
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time_sync_spin_threshold=100000
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[system]
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type=System
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children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
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children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
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mem_mode=timing
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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[system.dir_cntrl0]
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type=Directory_Controller
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@@ -52,32 +61,19 @@ version=0
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[system.l1_cntrl0]
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type=L1Cache_Controller
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children=sequencer
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L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
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L1IcacheMemory=system.l1_cntrl0.sequencer.icache
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children=L1DcacheMemory L1IcacheMemory
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L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
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L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
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buffer_size=0
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l2_select_num_bits=0
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number_of_TBEs=256
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recycle_latency=10
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request_latency=2
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sequencer=system.l1_cntrl0.sequencer
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sequencer=system.ruby.cpu_ruby_ports
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transitions_per_cycle=32
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version=0
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[system.l1_cntrl0.sequencer]
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type=RubySequencer
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children=dcache icache
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dcache=system.l1_cntrl0.sequencer.dcache
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deadlock_threshold=500000
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icache=system.l1_cntrl0.sequencer.icache
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=true
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version=0
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physMemPort=system.physmem.port[0]
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port=root.cpuPort[0]
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[system.l1_cntrl0.sequencer.dcache]
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[system.l1_cntrl0.L1DcacheMemory]
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type=RubyCache
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assoc=2
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latency=3
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@@ -85,7 +81,7 @@ replacement_policy=PSEUDO_LRU
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size=256
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start_index_bit=6
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[system.l1_cntrl0.sequencer.icache]
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[system.l1_cntrl0.L1IcacheMemory]
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type=RubyCache
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assoc=2
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latency=3
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@@ -121,14 +117,13 @@ latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.l1_cntrl0.sequencer.physMemPort
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port=system.ruby.cpu_ruby_ports.physMemPort
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[system.ruby]
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type=RubySystem
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children=debug network profiler tracer
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children=cpu_ruby_ports network profiler tracer
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block_size_bytes=64
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clock=1
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debug=system.ruby.debug
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mem_size=134217728
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network=system.ruby.network
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no_mem_vec=false
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@@ -138,13 +133,18 @@ randomization=true
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stats_filename=ruby.stats
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tracer=system.ruby.tracer
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[system.ruby.debug]
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type=RubyDebug
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filter_string=none
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output_filename=none
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protocol_trace=false
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start_time=1
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verbosity_string=none
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[system.ruby.cpu_ruby_ports]
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type=RubySequencer
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access_phys_mem=true
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dcache=system.l1_cntrl0.L1DcacheMemory
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deadlock_threshold=500000
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icache=system.l1_cntrl0.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=true
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version=0
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physMemPort=system.physmem.port[0]
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port=system.tester.cpuPort[0]
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[system.ruby.network]
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type=SimpleNetwork
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@@ -160,9 +160,9 @@ topology=system.ruby.network.topology
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[system.ruby.network.topology]
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type=Topology
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children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
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description=Crossbar
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ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
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int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
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name=Crossbar
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num_int_nodes=4
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print_config=false
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@@ -224,3 +224,10 @@ num_of_sequencers=1
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type=RubyTracer
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warmup_length=100000
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[system.tester]
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type=RubyTester
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checks_to_complete=100
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deadlock_threshold=50000
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wakeup_frequency=10
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cpuPort=system.ruby.cpu_ruby_ports.port[0]
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@@ -13,7 +13,7 @@ RubySystem config:
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Network Configuration
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---------------------
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network: SIMPLE_NETWORK
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topology: Crossbar
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topology:
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virtual_net_0: active, unordered
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virtual_net_1: active, unordered
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@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Aug/05/2010 10:40:25
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Real time: Feb/08/2011 17:41:43
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Profiler Stats
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--------------
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@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0.0166667
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Elapsed_time_in_hours: 0.000277778
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Elapsed_time_in_days: 1.15741e-05
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Virtual_time_in_seconds: 1.03
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Virtual_time_in_minutes: 0.0171667
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||||
Virtual_time_in_hours: 0.000286111
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||||
Virtual_time_in_days: 1.19213e-05
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Virtual_time_in_seconds: 0.8
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||||
Virtual_time_in_minutes: 0.0133333
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||||
Virtual_time_in_hours: 0.000222222
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Virtual_time_in_days: 9.25926e-06
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Ruby_current_time: 372291
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||||
Ruby_start_time: 0
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||||
Ruby_cycles: 372291
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||||
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mbytes_resident: 31.6016
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mbytes_total: 31.6094
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||||
resident_ratio: 1
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||||
mbytes_resident: 33.7734
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||||
mbytes_total: 208.148
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resident_ratio: 0.162313
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ruby_cycles_executed: [ 372292 ]
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@@ -119,8 +119,8 @@ Resource Usage
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page_size: 4096
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||||
user_time: 0
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||||
system_time: 0
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||||
page_reclaims: 7050
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||||
page_faults: 1907
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||||
page_reclaims: 9846
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||||
page_faults: 0
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||||
swaps: 0
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||||
block_inputs: 0
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||||
block_outputs: 0
|
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@@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.174693
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outgoing_messages_switch_3_link_2_Writeback_Control: 953 7624 [ 0 874 79 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_2_Unblock_Control: 880 7040 [ 0 0 880 0 0 0 0 0 0 0 ] base_latency: 1
|
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Cache Stats: system.l1_cntrl0.sequencer.icache
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system.l1_cntrl0.sequencer.icache_total_misses: 0
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||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
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||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
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||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
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||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
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Cache Stats: system.l1_cntrl0.L1IcacheMemory
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||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 0
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||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
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||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
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||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
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Cache Stats: system.l1_cntrl0.sequencer.dcache
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system.l1_cntrl0.sequencer.dcache_total_misses: 0
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||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
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||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
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system.l1_cntrl0.L1DcacheMemory_total_misses: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
--- L1Cache ---
|
||||
|
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@@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 10:34:54
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
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M5 started Aug 5 2010 10:40:24
|
||||
M5 executing on svvint09
|
||||
M5 compiled Feb 8 2011 17:41:34
|
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M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:41:42
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 210064 # Number of bytes of host memory used
|
||||
host_seconds 0.80 # Real time elapsed on the host
|
||||
host_tick_rate 465329 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213148 # Number of bytes of host memory used
|
||||
host_seconds 0.50 # Real time elapsed on the host
|
||||
host_tick_rate 746373 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000372 # Number of seconds simulated
|
||||
sim_ticks 372291 # Number of ticks simulated
|
||||
|
||||
@@ -1,13 +1,22 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
@@ -55,9 +64,9 @@ version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
@@ -69,24 +78,11 @@ no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
@@ -94,7 +90,7 @@ replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
@@ -132,14 +128,13 @@ latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
@@ -149,13 +144,18 @@ randomization=true
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.tester.cpuPort[0]
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
@@ -171,9 +171,9 @@ topology=system.ruby.network.topology
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
@@ -235,3 +235,10 @@ num_of_sequencers=1
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
wakeup_frequency=10
|
||||
cpuPort=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
|
||||
@@ -13,7 +13,7 @@ RubySystem config:
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: Crossbar
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, unordered
|
||||
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/05/2010 10:45:27
|
||||
Real time: Feb/08/2011 17:51:05
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
@@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.75
|
||||
Virtual_time_in_minutes: 0.0125
|
||||
Virtual_time_in_hours: 0.000208333
|
||||
Virtual_time_in_days: 8.68056e-06
|
||||
Virtual_time_in_seconds: 0.43
|
||||
Virtual_time_in_minutes: 0.00716667
|
||||
Virtual_time_in_hours: 0.000119444
|
||||
Virtual_time_in_days: 4.97685e-06
|
||||
|
||||
Ruby_current_time: 273851
|
||||
Ruby_current_time: 267511
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 273851
|
||||
Ruby_cycles: 267511
|
||||
|
||||
mbytes_resident: 31.5859
|
||||
mbytes_total: 31.5938
|
||||
resident_ratio: 1
|
||||
mbytes_resident: 33.7617
|
||||
mbytes_total: 208.121
|
||||
resident_ratio: 0.162259
|
||||
|
||||
ruby_cycles_executed: [ 273852 ]
|
||||
ruby_cycles_executed: [ 267512 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
@@ -66,17 +66,17 @@ Directory-0:0
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1015 average: 15.8108 | standard deviation: 1.12266 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 71 929 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 969 average: 15.8225 | standard deviation: 1.14181 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 53 902 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 256 max: 25954 count: 1000 average: 4306.83 | standard deviation: 6237.5 | 90 103 157 85 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1385 count: 59 average: 543.102 | standard deviation: 246.871 | 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 1 1 2 0 1 0 6 3 1 0 0 0 0 0 1 1 2 1 1 3 2 0 0 0 0 0 1 1 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 128 max: 21253 count: 41 average: 5185.15 | standard deviation: 6664.34 | 3 0 2 1 2 3 5 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 256 max: 25954 count: 900 average: 4513.56 | standard deviation: 6344.01 | 83 72 134 72 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 115 count: 78 average: 10.8205 | standard deviation: 28.5871 | 0 16 15 20 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ]
|
||||
miss_latency_L2Cache: [binsize: 8 max: 1002 count: 20 average: 461.5 | standard deviation: 273.391 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 256 max: 25954 count: 902 average: 4763.59 | standard deviation: 6403.26 | 6 96 154 81 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 64 max: 6580 count: 954 average: 4444.74 | standard deviation: 1862.02 | 67 9 3 1 6 4 9 12 10 7 1 8 5 1 3 0 1 1 1 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 2 0 4 2 0 3 3 7 8 7 10 19 13 19 31 34 41 31 33 38 49 47 50 44 30 44 35 33 34 26 17 12 12 14 21 8 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1214 count: 48 average: 548.458 | standard deviation: 260.39 | 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 1 0 0 0 0 1 3 0 0 0 0 0 0 0 1 1 0 0 1 2 1 2 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 2 1 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 32 max: 6135 count: 52 average: 4940.85 | standard deviation: 1334.03 | 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 2 0 1 0 1 0 2 1 0 1 1 0 2 1 0 6 1 0 3 1 1 0 1 1 0 1 1 2 1 0 0 0 0 1 1 0 1 2 0 2 0 1 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 6580 count: 854 average: 4633.53 | standard deviation: 1690.7 | 62 8 1 0 3 2 5 7 3 2 0 1 1 1 1 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 1 0 4 1 0 3 3 7 8 6 9 18 11 18 28 33 40 29 32 36 47 46 43 41 28 43 34 31 31 26 17 10 11 12 19 6 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 117 count: 73 average: 12.8356 | standard deviation: 32.0687 | 0 17 17 15 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 2 ]
|
||||
miss_latency_L2Cache: [binsize: 8 max: 812 count: 13 average: 309.154 | standard deviation: 223.678 | 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 64 max: 6580 count: 868 average: 4879.41 | standard deviation: 1307.99 | 0 0 1 1 4 2 7 12 10 6 1 8 4 1 3 0 1 1 1 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 2 0 4 2 0 3 3 7 8 7 10 19 13 19 31 34 41 31 33 38 49 47 50 44 30 44 35 33 34 26 17 12 12 14 21 8 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
@@ -86,16 +86,15 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 902
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 4 count: 1 average: 4 | standard deviation: 0 | 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 4 max: 568 count: 7 average: 329.571 | standard deviation: 182.864 | 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1385 count: 51 average: 582.98 | standard deviation: 229.926 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 0 1 0 1 0 6 3 1 0 0 0 0 0 0 1 2 1 1 3 2 0 0 0 0 0 1 0 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 3 average: 2.33333 | standard deviation: 1.22474 | 0 1 0 2 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 8 max: 843 count: 2 average: 551.5 | standard deviation: 412.244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 128 max: 21253 count: 36 average: 5874.47 | standard deviation: 6836.32 | 0 0 1 1 2 3 4 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 115 count: 74 average: 11.2568 | standard deviation: 29.2947 | 0 15 15 18 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 8 max: 1002 count: 11 average: 529.091 | standard deviation: 293.469 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 256 max: 25954 count: 815 average: 4976.13 | standard deviation: 6494.33 | 5 70 132 69 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
imcomplete_dir_Times: 868
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 108 count: 2 average: 55.5 | standard deviation: 74.2496 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 2 max: 359 count: 3 average: 181.333 | standard deviation: 165.7 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1214 count: 43 average: 597 | standard deviation: 225.443 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 1 1 0 0 1 2 1 2 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 2 1 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 3 average: 1.66667 | standard deviation: 0.707107 | 0 1 2 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 6135 count: 49 average: 5243.24 | standard deviation: 522.306 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 2 0 1 0 1 0 2 1 0 1 1 0 2 1 0 6 1 0 3 1 1 0 1 1 0 1 1 2 1 0 0 0 0 1 1 0 1 2 0 2 0 1 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 68 average: 12.0735 | standard deviation: 31.0217 | 0 16 15 14 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 2 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 8 max: 812 count: 10 average: 347.5 | standard deviation: 231.361 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 64 max: 6580 count: 776 average: 5093.73 | standard deviation: 906.859 | 0 0 0 0 1 1 3 7 3 1 0 1 0 1 1 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 1 0 4 1 0 3 3 7 8 6 9 18 11 18 28 33 40 29 32 36 47 46 43 41 28 43 34 31 31 26 17 10 11 12 19 6 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
@@ -127,8 +126,8 @@ Resource Usage
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7004
|
||||
page_faults: 1904
|
||||
page_reclaims: 9836
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
@@ -136,120 +135,116 @@ block_outputs: 0
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 5485 43880
|
||||
total_msg_count_Response_Data: 2871 206712
|
||||
total_msg_count_ResponseL2hit_Data: 51 3672
|
||||
total_msg_count_Response_Control: 9 72
|
||||
total_msg_count_Writeback_Data: 5349 385128
|
||||
total_msg_count_Writeback_Control: 246 1968
|
||||
total_msg_count_Persistent_Control: 2292 18336
|
||||
total_msgs: 16303 total_bytes: 659768
|
||||
total_msg_count_Request_Control: 5259 42072
|
||||
total_msg_count_Response_Data: 2727 196344
|
||||
total_msg_count_ResponseL2hit_Data: 33 2376
|
||||
total_msg_count_Response_Control: 3 24
|
||||
total_msg_count_Writeback_Data: 5187 373464
|
||||
total_msg_count_Writeback_Control: 234 1872
|
||||
total_msg_count_Persistent_Control: 2388 19104
|
||||
total_msgs: 15831 total_bytes: 635256
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.115928
|
||||
links_utilized_percent_switch_0_link_0: 0.0432124 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.188643 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.115486
|
||||
links_utilized_percent_switch_0_link_0: 0.0430356 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.187936 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 923 7384 [ 0 923 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 977 70344 [ 0 0 0 0 977 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 889 64008 [ 0 0 0 0 889 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 955 68760 [ 0 0 0 0 955 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.0997532
|
||||
links_utilized_percent_switch_1_link_0: 0.0435821 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.155924 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.0975123
|
||||
links_utilized_percent_switch_1_link_0: 0.0428627 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.152162 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 796 57312 [ 0 0 0 0 796 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 877 63144 [ 0 0 0 0 877 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 768 55296 [ 0 0 0 0 768 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.09541
|
||||
links_utilized_percent_switch_2_link_0: 0.040428 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.150392 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.0934167
|
||||
links_utilized_percent_switch_2_link_0: 0.0396432 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.14719 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 905 65160 [ 0 0 0 0 905 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 773 55656 [ 0 0 0 0 773 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 869 62568 [ 0 0 0 0 869 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.167305
|
||||
links_utilized_percent_switch_3_link_0: 0.165875 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.174328 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.161712 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 0.164909
|
||||
links_utilized_percent_switch_3_link_0: 0.164704 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.171451 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.158573 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 889 64008 [ 0 0 0 0 889 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 877 63144 [ 0 0 0 0 877 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 773 55656 [ 0 0 0 0 773 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 58
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 58
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 46
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 46
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 58 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 46 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 865
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 865
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 836
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 836
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_LD: 4.39306%
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_ST: 95.6069%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.86124%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.1388%
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 865 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 836 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [41 ] 41
|
||||
Ifetch [59 ] 59
|
||||
Store [901 ] 901
|
||||
Load [52 ] 52
|
||||
Ifetch [48 ] 48
|
||||
Store [855 ] 855
|
||||
Atomic [0 ] 0
|
||||
L1_Replacement [388292 ] 388292
|
||||
Data_Shared [9 ] 9
|
||||
Data_Owner [2 ] 2
|
||||
Data_All_Tokens [998 ] 998
|
||||
Ack [2 ] 2
|
||||
Ack_All_Tokens [2 ] 2
|
||||
L1_Replacement [19142 ] 19142
|
||||
Data_Shared [3 ] 3
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [976 ] 976
|
||||
Ack [1 ] 1
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_Local_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
@@ -259,21 +254,21 @@ Transient_Local_GETS_Last_Token [0 ] 0
|
||||
Persistent_GETX [0 ] 0
|
||||
Persistent_GETS [0 ] 0
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [382 ] 382
|
||||
Request_Timeout [674 ] 674
|
||||
Own_Lock_or_Unlock [398 ] 398
|
||||
Request_Timeout [783 ] 783
|
||||
Use_TimeoutStarverX [0 ] 0
|
||||
Use_TimeoutStarverS [0 ] 0
|
||||
Use_TimeoutNoStarvers [912 ] 912
|
||||
Use_TimeoutNoStarvers [877 ] 877
|
||||
Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [38 ] 38
|
||||
NP Ifetch [58 ] 58
|
||||
NP Store [826 ] 826
|
||||
NP Load [49 ] 49
|
||||
NP Ifetch [46 ] 46
|
||||
NP Store [787 ] 787
|
||||
NP Atomic [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
NP Data_All_Tokens [87 ] 87
|
||||
NP Data_All_Tokens [98 ] 98
|
||||
NP Ack [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_Local_GETX [0 ] 0
|
||||
@@ -282,7 +277,7 @@ NP Transient_Local_GETS [0 ] 0
|
||||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [175 ] 175
|
||||
NP Own_Lock_or_Unlock [190 ] 190
|
||||
|
||||
I Load [0 ] 0
|
||||
I Ifetch [0 ] 0
|
||||
@@ -305,10 +300,10 @@ I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [1 ] 1
|
||||
S Store [1 ] 1
|
||||
S Ifetch [2 ] 2
|
||||
S Store [0 ] 0
|
||||
S Atomic [0 ] 0
|
||||
S L1_Replacement [8 ] 8
|
||||
S L1_Replacement [3 ] 3
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
@@ -348,33 +343,33 @@ M Load [0 ] 0
|
||||
M Ifetch [0 ] 0
|
||||
M Store [0 ] 0
|
||||
M Atomic [0 ] 0
|
||||
M L1_Replacement [83 ] 83
|
||||
M L1_Replacement [88 ] 88
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_Local_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M Transient_Local_GETS [0 ] 0
|
||||
M Persistent_GETX [0 ] 0
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [12 ] 12
|
||||
M Own_Lock_or_Unlock [15 ] 15
|
||||
|
||||
MM Load [2 ] 2
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [64 ] 64
|
||||
MM Store [57 ] 57
|
||||
MM Atomic [0 ] 0
|
||||
MM L1_Replacement [826 ] 826
|
||||
MM L1_Replacement [786 ] 786
|
||||
MM Transient_GETX [0 ] 0
|
||||
MM Transient_Local_GETX [0 ] 0
|
||||
MM Transient_GETS [0 ] 0
|
||||
MM Transient_Local_GETS [0 ] 0
|
||||
MM Persistent_GETX [0 ] 0
|
||||
MM Persistent_GETS [0 ] 0
|
||||
MM Own_Lock_or_Unlock [27 ] 27
|
||||
MM Own_Lock_or_Unlock [15 ] 15
|
||||
|
||||
M_W Load [0 ] 0
|
||||
M_W Load [1 ] 1
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [1 ] 1
|
||||
M_W Atomic [0 ] 0
|
||||
M_W L1_Replacement [1338 ] 1338
|
||||
M_W L1_Replacement [396 ] 396
|
||||
M_W Transient_GETX [0 ] 0
|
||||
M_W Transient_Local_GETX [0 ] 0
|
||||
M_W Transient_GETS [0 ] 0
|
||||
@@ -384,35 +379,35 @@ M_W Persistent_GETS [0 ] 0
|
||||
M_W Own_Lock_or_Unlock [1 ] 1
|
||||
M_W Use_TimeoutStarverX [0 ] 0
|
||||
M_W Use_TimeoutStarverS [0 ] 0
|
||||
M_W Use_TimeoutNoStarvers [85 ] 85
|
||||
M_W Use_TimeoutNoStarvers [90 ] 90
|
||||
M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
MM_W Load [1 ] 1
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [9 ] 9
|
||||
MM_W Store [10 ] 10
|
||||
MM_W Atomic [0 ] 0
|
||||
MM_W L1_Replacement [30069 ] 30069
|
||||
MM_W L1_Replacement [7395 ] 7395
|
||||
MM_W Transient_GETX [0 ] 0
|
||||
MM_W Transient_Local_GETX [0 ] 0
|
||||
MM_W Transient_GETS [0 ] 0
|
||||
MM_W Transient_Local_GETS [0 ] 0
|
||||
MM_W Persistent_GETX [0 ] 0
|
||||
MM_W Persistent_GETS [0 ] 0
|
||||
MM_W Own_Lock_or_Unlock [26 ] 26
|
||||
MM_W Own_Lock_or_Unlock [25 ] 25
|
||||
MM_W Use_TimeoutStarverX [0 ] 0
|
||||
MM_W Use_TimeoutStarverS [0 ] 0
|
||||
MM_W Use_TimeoutNoStarvers [827 ] 827
|
||||
MM_W Use_TimeoutNoStarvers [787 ] 787
|
||||
MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Atomic [0 ] 0
|
||||
IM L1_Replacement [341249 ] 341249
|
||||
IM L1_Replacement [9791 ] 9791
|
||||
IM Data_Shared [0 ] 0
|
||||
IM Data_Owner [2 ] 2
|
||||
IM Data_All_Tokens [823 ] 823
|
||||
IM Ack [2 ] 2
|
||||
IM Data_Owner [0 ] 0
|
||||
IM Data_All_Tokens [786 ] 786
|
||||
IM Ack [1 ] 1
|
||||
IM Transient_GETX [0 ] 0
|
||||
IM Transient_Local_GETX [0 ] 0
|
||||
IM Transient_GETS [0 ] 0
|
||||
@@ -422,8 +417,8 @@ IM Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IM Persistent_GETX [0 ] 0
|
||||
IM Persistent_GETS [0 ] 0
|
||||
IM Persistent_GETS_Last_Token [0 ] 0
|
||||
IM Own_Lock_or_Unlock [124 ] 124
|
||||
IM Request_Timeout [608 ] 608
|
||||
IM Own_Lock_or_Unlock [135 ] 135
|
||||
IM Request_Timeout [709 ] 709
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
@@ -432,7 +427,7 @@ SM Atomic [0 ] 0
|
||||
SM L1_Replacement [0 ] 0
|
||||
SM Data_Shared [0 ] 0
|
||||
SM Data_Owner [0 ] 0
|
||||
SM Data_All_Tokens [1 ] 1
|
||||
SM Data_All_Tokens [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Transient_GETX [0 ] 0
|
||||
SM Transient_Local_GETX [0 ] 0
|
||||
@@ -454,7 +449,7 @@ OM L1_Replacement [0 ] 0
|
||||
OM Data_Shared [0 ] 0
|
||||
OM Data_All_Tokens [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM Ack_All_Tokens [2 ] 2
|
||||
OM Ack_All_Tokens [0 ] 0
|
||||
OM Transient_GETX [0 ] 0
|
||||
OM Transient_Local_GETX [0 ] 0
|
||||
OM Transient_GETS [0 ] 0
|
||||
@@ -464,17 +459,17 @@ OM Transient_Local_GETS_Last_Token [0 ] 0
|
||||
OM Persistent_GETX [0 ] 0
|
||||
OM Persistent_GETS [0 ] 0
|
||||
OM Persistent_GETS_Last_Token [0 ] 0
|
||||
OM Own_Lock_or_Unlock [1 ] 1
|
||||
OM Request_Timeout [1 ] 1
|
||||
OM Own_Lock_or_Unlock [0 ] 0
|
||||
OM Request_Timeout [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Atomic [0 ] 0
|
||||
IS L1_Replacement [14719 ] 14719
|
||||
IS Data_Shared [9 ] 9
|
||||
IS L1_Replacement [683 ] 683
|
||||
IS Data_Shared [3 ] 3
|
||||
IS Data_Owner [0 ] 0
|
||||
IS Data_All_Tokens [87 ] 87
|
||||
IS Data_All_Tokens [92 ] 92
|
||||
IS Ack [0 ] 0
|
||||
IS Transient_GETX [0 ] 0
|
||||
IS Transient_Local_GETX [0 ] 0
|
||||
@@ -485,8 +480,8 @@ IS Transient_Local_GETS_Last_Token [0 ] 0
|
||||
IS Persistent_GETX [0 ] 0
|
||||
IS Persistent_GETS [0 ] 0
|
||||
IS Persistent_GETS_Last_Token [0 ] 0
|
||||
IS Own_Lock_or_Unlock [16 ] 16
|
||||
IS Request_Timeout [65 ] 65
|
||||
IS Own_Lock_or_Unlock [17 ] 17
|
||||
IS Request_Timeout [74 ] 74
|
||||
|
||||
I_L Load [0 ] 0
|
||||
I_L Ifetch [0 ] 0
|
||||
@@ -590,50 +585,50 @@ IS_L Own_Lock_or_Unlock [0 ] 0
|
||||
IS_L Request_Timeout [0 ] 0
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 906
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 906
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 871
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 871
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 9.60265%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 90.3974%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 10.5626%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.4374%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 906 100%
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 871 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [95 ] 95
|
||||
L1_GETS_Last_Token [1 ] 1
|
||||
L1_GETX [826 ] 826
|
||||
L1_GETS_Last_Token [0 ] 0
|
||||
L1_GETX [787 ] 787
|
||||
L1_INV [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
L2_Replacement [857 ] 857
|
||||
L2_Replacement [799 ] 799
|
||||
Writeback_Tokens [0 ] 0
|
||||
Writeback_Shared_Data [8 ] 8
|
||||
Writeback_All_Tokens [908 ] 908
|
||||
Writeback_Shared_Data [3 ] 3
|
||||
Writeback_All_Tokens [874 ] 874
|
||||
Writeback_Owned [0 ] 0
|
||||
Data_Shared [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Persistent_GETX [173 ] 173
|
||||
Persistent_GETS [18 ] 18
|
||||
Persistent_GETX [179 ] 179
|
||||
Persistent_GETS [20 ] 20
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [191 ] 191
|
||||
Own_Lock_or_Unlock [199 ] 199
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [87 ] 87
|
||||
NP L1_GETX [816 ] 816
|
||||
NP L1_GETS [92 ] 92
|
||||
NP L1_GETX [777 ] 777
|
||||
NP L1_INV [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Writeback_Tokens [0 ] 0
|
||||
NP Writeback_Shared_Data [7 ] 7
|
||||
NP Writeback_All_Tokens [852 ] 852
|
||||
NP Writeback_Shared_Data [3 ] 3
|
||||
NP Writeback_All_Tokens [798 ] 798
|
||||
NP Writeback_Owned [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
@@ -642,7 +637,7 @@ NP Ack [0 ] 0
|
||||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [168 ] 168
|
||||
NP Own_Lock_or_Unlock [181 ] 181
|
||||
|
||||
I L1_GETS [0 ] 0
|
||||
I L1_GETS_Last_Token [0 ] 0
|
||||
@@ -651,10 +646,10 @@ I L1_INV [0 ] 0
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I L2_Replacement [28 ] 28
|
||||
I L2_Replacement [24 ] 24
|
||||
I Writeback_Tokens [0 ] 0
|
||||
I Writeback_Shared_Data [1 ] 1
|
||||
I Writeback_All_Tokens [5 ] 5
|
||||
I Writeback_Shared_Data [0 ] 0
|
||||
I Writeback_All_Tokens [3 ] 3
|
||||
I Writeback_Owned [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
@@ -666,13 +661,13 @@ I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S L1_GETS [0 ] 0
|
||||
S L1_GETS_Last_Token [1 ] 1
|
||||
S L1_GETX [2 ] 2
|
||||
S L1_GETS_Last_Token [0 ] 0
|
||||
S L1_GETX [1 ] 1
|
||||
S L1_INV [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S L2_Replacement [5 ] 5
|
||||
S L2_Replacement [2 ] 2
|
||||
S Writeback_Tokens [0 ] 0
|
||||
S Writeback_Shared_Data [0 ] 0
|
||||
S Writeback_All_Tokens [0 ] 0
|
||||
@@ -688,12 +683,12 @@ S Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
O L1_GETS [0 ] 0
|
||||
O L1_GETS_Last_Token [0 ] 0
|
||||
O L1_GETX [1 ] 1
|
||||
O L1_GETX [0 ] 0
|
||||
O L1_INV [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O L2_Replacement [7 ] 7
|
||||
O L2_Replacement [3 ] 3
|
||||
O Writeback_Tokens [0 ] 0
|
||||
O Writeback_Shared_Data [0 ] 0
|
||||
O Writeback_All_Tokens [0 ] 0
|
||||
@@ -706,34 +701,34 @@ O Persistent_GETS [0 ] 0
|
||||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M L1_GETS [8 ] 8
|
||||
M L1_GETX [7 ] 7
|
||||
M L1_GETS [3 ] 3
|
||||
M L1_GETX [8 ] 8
|
||||
M L1_INV [0 ] 0
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M L2_Replacement [814 ] 814
|
||||
M Persistent_GETX [26 ] 26
|
||||
M L2_Replacement [768 ] 768
|
||||
M Persistent_GETX [20 ] 20
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I_L L1_GETS [0 ] 0
|
||||
I_L L1_GETX [0 ] 0
|
||||
I_L L1_GETX [1 ] 1
|
||||
I_L L1_INV [0 ] 0
|
||||
I_L Transient_GETX [0 ] 0
|
||||
I_L Transient_GETS [0 ] 0
|
||||
I_L Transient_GETS_Last_Token [0 ] 0
|
||||
I_L L2_Replacement [3 ] 3
|
||||
I_L L2_Replacement [2 ] 2
|
||||
I_L Writeback_Tokens [0 ] 0
|
||||
I_L Writeback_Shared_Data [0 ] 0
|
||||
I_L Writeback_All_Tokens [51 ] 51
|
||||
I_L Writeback_All_Tokens [73 ] 73
|
||||
I_L Writeback_Owned [0 ] 0
|
||||
I_L Data_Shared [0 ] 0
|
||||
I_L Data_Owner [0 ] 0
|
||||
I_L Data_All_Tokens [0 ] 0
|
||||
I_L Ack [0 ] 0
|
||||
I_L Persistent_GETX [147 ] 147
|
||||
I_L Persistent_GETS [18 ] 18
|
||||
I_L Own_Lock_or_Unlock [23 ] 23
|
||||
I_L Persistent_GETX [159 ] 159
|
||||
I_L Persistent_GETS [20 ] 20
|
||||
I_L Own_Lock_or_Unlock [18 ] 18
|
||||
|
||||
S_L L1_GETS [0 ] 0
|
||||
S_L L1_GETS_Last_Token [0 ] 0
|
||||
@@ -757,93 +752,93 @@ S_L Persistent_GETS_Last_Token [0 ] 0
|
||||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1720
|
||||
memory_reads: 902
|
||||
memory_writes: 818
|
||||
memory_refreshes: 571
|
||||
memory_total_request_delays: 1302
|
||||
memory_delays_per_request: 0.756977
|
||||
memory_delays_in_input_queue: 202
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1100
|
||||
memory_stalls_for_bank_busy: 220
|
||||
memory_total_requests: 1655
|
||||
memory_reads: 869
|
||||
memory_writes: 786
|
||||
memory_refreshes: 558
|
||||
memory_total_request_delays: 1116
|
||||
memory_delays_per_request: 0.67432
|
||||
memory_delays_in_input_queue: 156
|
||||
memory_delays_behind_head_of_bank_queue: 3
|
||||
memory_delays_stalled_at_head_of_bank_queue: 957
|
||||
memory_stalls_for_bank_busy: 245
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 97
|
||||
memory_stalls_for_bus: 424
|
||||
memory_stalls_for_arbitration: 76
|
||||
memory_stalls_for_bus: 363
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 268
|
||||
memory_stalls_for_read_read_turnaround: 91
|
||||
accesses_per_bank: 61 42 48 69 122 69 58 56 55 51 54 41 43 47 55 55 46 45 53 50 43 51 55 52 43 56 60 54 49 40 40 57
|
||||
memory_stalls_for_read_write_turnaround: 197
|
||||
memory_stalls_for_read_read_turnaround: 76
|
||||
accesses_per_bank: 42 44 54 72 110 62 62 43 42 53 38 40 51 47 54 42 48 54 39 56 64 58 51 54 48 46 43 52 46 43 49 48
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [828 ] 828
|
||||
GETS [87 ] 87
|
||||
Lockdown [191 ] 191
|
||||
Unlockdown [191 ] 191
|
||||
GETX [807 ] 807
|
||||
GETS [92 ] 92
|
||||
Lockdown [199 ] 199
|
||||
Unlockdown [199 ] 199
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
Data_Owner [7 ] 7
|
||||
Data_All_Tokens [825 ] 825
|
||||
Data_Owner [3 ] 3
|
||||
Data_All_Tokens [790 ] 790
|
||||
Ack_Owner [0 ] 0
|
||||
Ack_Owner_All_Tokens [76 ] 76
|
||||
Tokens [2 ] 2
|
||||
Ack_All_Tokens [3 ] 3
|
||||
Tokens [0 ] 0
|
||||
Ack_All_Tokens [2 ] 2
|
||||
Request_Timeout [0 ] 0
|
||||
Memory_Data [902 ] 902
|
||||
Memory_Ack [817 ] 817
|
||||
Memory_Data [868 ] 868
|
||||
Memory_Ack [786 ] 786
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
O GETX [811 ] 811
|
||||
O GETS [83 ] 83
|
||||
O Lockdown [6 ] 6
|
||||
O GETX [773 ] 773
|
||||
O GETS [90 ] 90
|
||||
O Lockdown [5 ] 5
|
||||
O Unlockdown [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
O Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O Data_Owner [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Tokens [0 ] 0
|
||||
O Ack_All_Tokens [3 ] 3
|
||||
O Ack_All_Tokens [2 ] 2
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO GETX [8 ] 8
|
||||
NO GETS [4 ] 4
|
||||
NO Lockdown [168 ] 168
|
||||
NO GETX [2 ] 2
|
||||
NO GETS [2 ] 2
|
||||
NO Lockdown [180 ] 180
|
||||
NO Unlockdown [0 ] 0
|
||||
NO Own_Lock_or_Unlock [0 ] 0
|
||||
NO Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO Data_Owner [7 ] 7
|
||||
NO Data_All_Tokens [811 ] 811
|
||||
NO Data_Owner [3 ] 3
|
||||
NO Data_All_Tokens [783 ] 783
|
||||
NO Ack_Owner [0 ] 0
|
||||
NO Ack_Owner_All_Tokens [76 ] 76
|
||||
NO Tokens [1 ] 1
|
||||
NO Tokens [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
||||
L GETX [0 ] 0
|
||||
L GETX [4 ] 4
|
||||
L GETS [0 ] 0
|
||||
L Lockdown [0 ] 0
|
||||
L Unlockdown [189 ] 189
|
||||
L Unlockdown [199 ] 199
|
||||
L Own_Lock_or_Unlock [0 ] 0
|
||||
L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L Data_Owner [0 ] 0
|
||||
L Data_All_Tokens [14 ] 14
|
||||
L Data_All_Tokens [7 ] 7
|
||||
L Ack_Owner [0 ] 0
|
||||
L Ack_Owner_All_Tokens [0 ] 0
|
||||
L Tokens [1 ] 1
|
||||
L Tokens [0 ] 0
|
||||
L DMA_READ [0 ] 0
|
||||
L DMA_WRITE [0 ] 0
|
||||
L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_W GETX [9 ] 9
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
O_W Lockdown [3 ] 3
|
||||
O_W Lockdown [1 ] 1
|
||||
O_W Unlockdown [0 ] 0
|
||||
O_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
@@ -852,16 +847,16 @@ O_W Data_All_Tokens [0 ] 0
|
||||
O_W Ack_Owner [0 ] 0
|
||||
O_W Tokens [0 ] 0
|
||||
O_W Ack_All_Tokens [0 ] 0
|
||||
O_W Memory_Data [1 ] 1
|
||||
O_W Memory_Ack [815 ] 815
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W Memory_Ack [785 ] 785
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_O_W GETX [0 ] 0
|
||||
L_O_W GETX [28 ] 28
|
||||
L_O_W GETS [0 ] 0
|
||||
L_O_W Lockdown [0 ] 0
|
||||
L_O_W Unlockdown [2 ] 2
|
||||
L_O_W Unlockdown [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L_O_W Data_Owner [0 ] 0
|
||||
@@ -869,8 +864,8 @@ L_O_W Data_All_Tokens [0 ] 0
|
||||
L_O_W Ack_Owner [0 ] 0
|
||||
L_O_W Tokens [0 ] 0
|
||||
L_O_W Ack_All_Tokens [0 ] 0
|
||||
L_O_W Memory_Data [7 ] 7
|
||||
L_O_W Memory_Ack [2 ] 2
|
||||
L_O_W Memory_Data [6 ] 6
|
||||
L_O_W Memory_Ack [1 ] 1
|
||||
L_O_W DMA_READ [0 ] 0
|
||||
L_O_W DMA_WRITE [0 ] 0
|
||||
L_O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
@@ -886,7 +881,7 @@ L_NO_W Data_All_Tokens [0 ] 0
|
||||
L_NO_W Ack_Owner [0 ] 0
|
||||
L_NO_W Tokens [0 ] 0
|
||||
L_NO_W Ack_All_Tokens [0 ] 0
|
||||
L_NO_W Memory_Data [14 ] 14
|
||||
L_NO_W Memory_Data [13 ] 13
|
||||
L_NO_W DMA_READ [0 ] 0
|
||||
L_NO_W DMA_WRITE [0 ] 0
|
||||
L_NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
@@ -927,7 +922,7 @@ DW_L_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W Lockdown [14 ] 14
|
||||
NO_W Lockdown [13 ] 13
|
||||
NO_W Unlockdown [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
@@ -936,7 +931,7 @@ NO_W Data_All_Tokens [0 ] 0
|
||||
NO_W Ack_Owner [0 ] 0
|
||||
NO_W Tokens [0 ] 0
|
||||
NO_W Ack_All_Tokens [0 ] 0
|
||||
NO_W Memory_Data [880 ] 880
|
||||
NO_W Memory_Data [849 ] 849
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 10:41:36
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:45:27
|
||||
M5 executing on svvint09
|
||||
M5 compiled Feb 8 2011 17:50:56
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:51:05
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 273851 because Ruby Tester completed
|
||||
Exiting @ tick 267511 because Ruby Tester completed
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 210052 # Number of bytes of host memory used
|
||||
host_seconds 0.53 # Real time elapsed on the host
|
||||
host_tick_rate 516678 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213120 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_tick_rate 1663377 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000274 # Number of seconds simulated
|
||||
sim_ticks 273851 # Number of ticks simulated
|
||||
sim_seconds 0.000268 # Number of seconds simulated
|
||||
sim_ticks 267511 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,19 +1,29 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
children=dir_cntrl0 l1_cntrl0 physmem ruby tester
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer probeFilter
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
full_bit_dir_enabled=false
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
@@ -62,17 +72,18 @@ start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
children=L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
|
||||
L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
|
||||
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
@@ -84,35 +95,6 @@ replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
@@ -121,14 +103,13 @@ latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
@@ -138,13 +119,35 @@ randomization=true
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
access_phys_mem=true
|
||||
dcache=system.ruby.cpu_ruby_ports.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.tester.cpuPort[0]
|
||||
|
||||
[system.ruby.cpu_ruby_ports.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.cpu_ruby_ports.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
@@ -160,9 +163,9 @@ topology=system.ruby.network.topology
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
name=Crossbar
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
@@ -208,3 +211,10 @@ num_of_sequencers=1
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
wakeup_frequency=10
|
||||
cpuPort=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
|
||||
@@ -13,7 +13,7 @@ RubySystem config:
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: Crossbar
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/05/2010 14:46:32
|
||||
Real time: Feb/08/2011 17:57:03
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
@@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.69
|
||||
Virtual_time_in_minutes: 0.0115
|
||||
Virtual_time_in_hours: 0.000191667
|
||||
Virtual_time_in_days: 7.98611e-06
|
||||
Virtual_time_in_seconds: 0.4
|
||||
Virtual_time_in_minutes: 0.00666667
|
||||
Virtual_time_in_hours: 0.000111111
|
||||
Virtual_time_in_days: 4.62963e-06
|
||||
|
||||
Ruby_current_time: 213851
|
||||
Ruby_current_time: 210961
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 213851
|
||||
Ruby_cycles: 210961
|
||||
|
||||
mbytes_resident: 31.293
|
||||
mbytes_total: 31.3008
|
||||
resident_ratio: 1
|
||||
mbytes_resident: 33.4023
|
||||
mbytes_total: 207.566
|
||||
resident_ratio: 0.160961
|
||||
|
||||
ruby_cycles_executed: [ 213852 ]
|
||||
ruby_cycles_executed: [ 210962 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
@@ -65,17 +65,17 @@ Directory-0:0
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 963 average: 15.8069 | standard deviation: 1.15034 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 65 883 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 978 average: 15.8016 | standard deviation: 1.14461 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 71 891 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 128 max: 23081 count: 948 average: 3529.13 | standard deviation: 5116.76 | 71 12 47 82 73 59 68 59 47 38 28 25 17 14 12 7 10 4 1 9 4 5 5 7 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 4 4 5 5 1 4 3 3 3 3 3 3 4 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1215 count: 59 average: 478.39 | standard deviation: 246.067 | 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 128 max: 15642 count: 41 average: 3000.32 | standard deviation: 4886.74 | 5 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 128 max: 23081 count: 848 average: 3766.95 | standard deviation: 5236.59 | 61 10 32 62 58 52 60 56 43 35 27 24 17 14 12 5 10 4 0 9 4 5 5 6 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 4 3 4 4 1 4 3 3 3 3 3 3 4 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 118 count: 65 average: 15.8923 | standard deviation: 35.394 | 0 9 14 16 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_L2Cache: [binsize: 128 max: 19544 count: 29 average: 3519.03 | standard deviation: 5619.12 | 6 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 128 max: 23081 count: 854 average: 3796.87 | standard deviation: 5197.84 | 0 10 46 78 72 57 67 59 47 38 27 25 16 14 12 7 10 3 1 9 4 5 5 6 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 3 4 5 4 1 4 3 3 3 3 3 3 3 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 64 max: 8993 count: 963 average: 3469.42 | standard deviation: 1599.67 | 72 11 5 3 10 7 13 12 7 12 1 8 4 1 1 2 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 6 10 12 7 16 18 17 32 34 24 31 26 29 36 35 35 28 41 44 32 34 21 30 17 25 22 20 20 10 10 6 8 9 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1126 count: 52 average: 473.327 | standard deviation: 221.338 | 0 2 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 5235 count: 48 average: 3979.79 | standard deviation: 1306.56 | 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 8993 count: 863 average: 3621.56 | standard deviation: 1476.69 | 66 9 4 1 5 2 6 6 3 6 0 0 2 1 1 2 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 5 10 11 7 16 18 17 32 31 23 31 25 28 35 30 31 23 40 43 29 34 20 27 16 25 22 19 19 7 8 6 5 8 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 117 count: 71 average: 13.3803 | standard deviation: 32.5601 | 0 10 15 23 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ]
|
||||
miss_latency_L2Cache: [binsize: 64 max: 8993 count: 33 average: 2589.88 | standard deviation: 2554.56 | 8 4 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 6151 count: 859 average: 3788.87 | standard deviation: 1226.92 | 0 0 0 0 0 5 1 1 8 2 2 5 13 0 0 12 6 0 4 8 1 0 7 1 1 3 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 3 6 3 4 7 4 3 6 10 11 6 4 12 14 14 15 17 13 9 17 13 7 19 18 10 17 19 20 15 17 17 8 20 25 16 22 22 14 18 15 19 10 10 19 11 9 8 14 11 15 7 12 8 9 11 5 5 4 6 3 3 3 5 4 5 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
@@ -85,15 +85,14 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 854
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2 average: 2.5 | standard deviation: 1 | 0 0 1 1 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 123 count: 3 average: 50 | standard deviation: 63.2218 | 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1215 count: 54 average: 519.815 | standard deviation: 213.139 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 4 count: 5 average: 3 | standard deviation: 0.707107 | 0 0 1 3 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 128 max: 15642 count: 36 average: 3416.61 | standard deviation: 5082.33 | 0 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 118 count: 58 average: 17.4655 | standard deviation: 37.1906 | 0 9 12 12 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 128 max: 19544 count: 26 average: 3919.31 | standard deviation: 5809.69 | 3 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 128 max: 23081 count: 764 average: 4046.41 | standard deviation: 5309.16 | 0 8 31 58 57 50 59 56 43 35 26 24 16 14 12 5 10 3 0 9 4 5 5 5 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 3 3 4 3 1 4 3 3 3 3 3 3 3 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
imcomplete_dir_Times: 859
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 117 count: 4 average: 62.25 | standard deviation: 62.0725 | 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1126 count: 48 average: 507.583 | standard deviation: 193.22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 4 average: 2 | standard deviation: 0.816497 | 0 1 2 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 5235 count: 44 average: 4341.41 | standard deviation: 510.099 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 67 average: 14.0597 | standard deviation: 33.4075 | 0 9 13 22 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 64 max: 8993 count: 29 average: 2938.52 | standard deviation: 2533.58 | 6 2 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 6151 count: 767 average: 3962.52 | standard deviation: 973.04 | 0 0 0 0 0 4 0 0 4 1 0 2 6 0 0 6 2 0 1 5 0 0 0 0 0 2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 2 6 3 4 6 4 3 6 10 11 6 4 12 14 14 13 16 13 8 17 13 6 19 17 10 16 19 18 12 15 15 7 16 25 15 22 21 13 16 15 19 9 10 17 10 8 8 14 11 15 7 12 7 9 10 5 2 4 4 3 3 3 2 4 4 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
@@ -125,8 +124,8 @@ Resource Usage
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 6929
|
||||
page_faults: 1882
|
||||
page_reclaims: 9722
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
@@ -134,117 +133,118 @@ block_outputs: 0
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 2568 20544
|
||||
total_msg_count_Response_Data: 2562 184464
|
||||
total_msg_count_Writeback_Data: 2281 164232
|
||||
total_msg_count_Writeback_Control: 5351 42808
|
||||
total_msg_count_Unblock_Control: 2559 20472
|
||||
total_msgs: 15321 total_bytes: 432520
|
||||
total_msg_count_Request_Control: 2577 20616
|
||||
total_msg_count_Response_Data: 2577 185544
|
||||
total_msg_count_Writeback_Data: 2301 165672
|
||||
total_msg_count_Writeback_Control: 5367 42936
|
||||
total_msg_count_Unblock_Control: 2574 20592
|
||||
total_msgs: 15396 total_bytes: 435360
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.13593
|
||||
links_utilized_percent_switch_0_link_0: 0.0498829 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.221977 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.138684
|
||||
links_utilized_percent_switch_0_link_0: 0.0508566 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.226511 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 761 54792 [ 0 0 0 0 0 761 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 936 7488 [ 0 0 849 0 0 87 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.127495
|
||||
links_utilized_percent_switch_1_link_0: 0.0554358 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.199555 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.130027
|
||||
links_utilized_percent_switch_1_link_0: 0.0566278 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.203426 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 849 6792 [ 0 0 0 849 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.210637
|
||||
links_utilized_percent_switch_2_link_0: 0.199531 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.221743 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.214969
|
||||
links_utilized_percent_switch_2_link_0: 0.203426 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.226511 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 57
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 57
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.icache
|
||||
system.ruby.cpu_ruby_ports.icache_total_misses: 52
|
||||
system.ruby.cpu_ruby_ports.icache_total_demand_misses: 52
|
||||
system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
|
||||
system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 57 100%
|
||||
system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 52 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 840
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 840
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_total_misses: 852
|
||||
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 852
|
||||
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_LD: 4.28571%
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_ST: 95.7143%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 5.28169%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 94.7183%
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 840 100%
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 852 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L2cacheMemory
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 856
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 856
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 904
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 904
|
||||
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.20561%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.486%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 6.30841%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.97788%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.2699%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.75221%
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 856 100%
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 904 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [41 ] 41
|
||||
Ifetch [106 ] 106
|
||||
Store [906 ] 906
|
||||
L2_Replacement [849 ] 849
|
||||
L1_to_L2 [303164 ] 303164
|
||||
Trigger_L2_to_L1D [38 ] 38
|
||||
Trigger_L2_to_L1I [3 ] 3
|
||||
Complete_L2_to_L1 [41 ] 41
|
||||
Load [48 ] 48
|
||||
Ifetch [53 ] 53
|
||||
Store [888 ] 888
|
||||
L2_Replacement [854 ] 854
|
||||
L1_to_L2 [16074 ] 16074
|
||||
Trigger_L2_to_L1D [39 ] 39
|
||||
Trigger_L2_to_L1I [4 ] 4
|
||||
Complete_L2_to_L1 [43 ] 43
|
||||
Other_GETX [0 ] 0
|
||||
Other_GETS [0 ] 0
|
||||
Merged_GETS [0 ] 0
|
||||
Other_GETS_No_Mig [0 ] 0
|
||||
NC_DMA_GETS [0 ] 0
|
||||
Invalidate [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Data [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Exclusive_Data [854 ] 854
|
||||
Writeback_Ack [848 ] 848
|
||||
Exclusive_Data [859 ] 859
|
||||
Writeback_Ack [852 ] 852
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [0 ] 0
|
||||
All_acks_no_sharers [853 ] 853
|
||||
All_acks_no_sharers [859 ] 859
|
||||
|
||||
- Transitions -
|
||||
I Load [36 ] 36
|
||||
I Ifetch [54 ] 54
|
||||
I Store [766 ] 766
|
||||
I Load [44 ] 44
|
||||
I Ifetch [48 ] 48
|
||||
I Store [769 ] 769
|
||||
I L2_Replacement [0 ] 0
|
||||
I L1_to_L2 [0 ] 0
|
||||
I Trigger_L2_to_L1D [0 ] 0
|
||||
@@ -252,6 +252,7 @@ I Trigger_L2_to_L1I [0 ] 0
|
||||
I Other_GETX [0 ] 0
|
||||
I Other_GETS [0 ] 0
|
||||
I Other_GETS_No_Mig [0 ] 0
|
||||
I NC_DMA_GETS [0 ] 0
|
||||
I Invalidate [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
@@ -264,6 +265,7 @@ S Trigger_L2_to_L1I [0 ] 0
|
||||
S Other_GETX [0 ] 0
|
||||
S Other_GETS [0 ] 0
|
||||
S Other_GETS_No_Mig [0 ] 0
|
||||
S NC_DMA_GETS [0 ] 0
|
||||
S Invalidate [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
@@ -277,46 +279,50 @@ O Other_GETX [0 ] 0
|
||||
O Other_GETS [0 ] 0
|
||||
O Merged_GETS [0 ] 0
|
||||
O Other_GETS_No_Mig [0 ] 0
|
||||
O NC_DMA_GETS [0 ] 0
|
||||
O Invalidate [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [1 ] 1
|
||||
M Store [1 ] 1
|
||||
M L2_Replacement [87 ] 87
|
||||
M L1_to_L2 [88 ] 88
|
||||
M Trigger_L2_to_L1D [1 ] 1
|
||||
M Ifetch [0 ] 0
|
||||
M Store [3 ] 3
|
||||
M L2_Replacement [85 ] 85
|
||||
M L1_to_L2 [95 ] 95
|
||||
M Trigger_L2_to_L1D [9 ] 9
|
||||
M Trigger_L2_to_L1I [0 ] 0
|
||||
M Other_GETX [0 ] 0
|
||||
M Other_GETS [0 ] 0
|
||||
M Merged_GETS [0 ] 0
|
||||
M Other_GETS_No_Mig [0 ] 0
|
||||
M NC_DMA_GETS [0 ] 0
|
||||
M Invalidate [0 ] 0
|
||||
|
||||
MM Load [5 ] 5
|
||||
MM Load [4 ] 4
|
||||
MM Ifetch [4 ] 4
|
||||
MM Store [82 ] 82
|
||||
MM L2_Replacement [762 ] 762
|
||||
MM Store [92 ] 92
|
||||
MM L2_Replacement [769 ] 769
|
||||
MM L1_to_L2 [804 ] 804
|
||||
MM Trigger_L2_to_L1D [37 ] 37
|
||||
MM Trigger_L2_to_L1I [3 ] 3
|
||||
MM Trigger_L2_to_L1D [30 ] 30
|
||||
MM Trigger_L2_to_L1I [4 ] 4
|
||||
MM Other_GETX [0 ] 0
|
||||
MM Other_GETS [0 ] 0
|
||||
MM Merged_GETS [0 ] 0
|
||||
MM Other_GETS_No_Mig [0 ] 0
|
||||
MM NC_DMA_GETS [0 ] 0
|
||||
MM Invalidate [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L1_to_L2 [275518 ] 275518
|
||||
IM L1_to_L2 [9842 ] 9842
|
||||
IM Other_GETX [0 ] 0
|
||||
IM Other_GETS [0 ] 0
|
||||
IM Other_GETS_No_Mig [0 ] 0
|
||||
IM NC_DMA_GETS [0 ] 0
|
||||
IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [764 ] 764
|
||||
IM Exclusive_Data [767 ] 767
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
@@ -326,9 +332,11 @@ SM L1_to_L2 [0 ] 0
|
||||
SM Other_GETX [0 ] 0
|
||||
SM Other_GETS [0 ] 0
|
||||
SM Other_GETS_No_Mig [0 ] 0
|
||||
SM NC_DMA_GETS [0 ] 0
|
||||
SM Invalidate [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Data [0 ] 0
|
||||
SM Exclusive_Data [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
@@ -339,6 +347,7 @@ OM Other_GETX [0 ] 0
|
||||
OM Other_GETS [0 ] 0
|
||||
OM Merged_GETS [0 ] 0
|
||||
OM Other_GETS_No_Mig [0 ] 0
|
||||
OM NC_DMA_GETS [0 ] 0
|
||||
OM Invalidate [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM All_acks [0 ] 0
|
||||
@@ -354,34 +363,35 @@ ISM All_acks_no_sharers [0 ] 0
|
||||
|
||||
M_W Load [0 ] 0
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W Store [1 ] 1
|
||||
M_W L2_Replacement [0 ] 0
|
||||
M_W L1_to_L2 [483 ] 483
|
||||
M_W L1_to_L2 [310 ] 310
|
||||
M_W Ack [0 ] 0
|
||||
M_W All_acks_no_sharers [89 ] 89
|
||||
M_W All_acks_no_sharers [91 ] 91
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [1 ] 1
|
||||
MM_W Store [0 ] 0
|
||||
MM_W L2_Replacement [0 ] 0
|
||||
MM_W L1_to_L2 [10887 ] 10887
|
||||
MM_W L1_to_L2 [4284 ] 4284
|
||||
MM_W Ack [0 ] 0
|
||||
MM_W All_acks_no_sharers [764 ] 764
|
||||
MM_W All_acks_no_sharers [768 ] 768
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L1_to_L2 [14644 ] 14644
|
||||
IS L1_to_L2 [621 ] 621
|
||||
IS Other_GETX [0 ] 0
|
||||
IS Other_GETS [0 ] 0
|
||||
IS Other_GETS_No_Mig [0 ] 0
|
||||
IS NC_DMA_GETS [0 ] 0
|
||||
IS Invalidate [0 ] 0
|
||||
IS Ack [0 ] 0
|
||||
IS Shared_Ack [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Shared_Data [0 ] 0
|
||||
IS Exclusive_Data [90 ] 90
|
||||
IS Exclusive_Data [92 ] 92
|
||||
|
||||
SS Load [0 ] 0
|
||||
SS Ifetch [0 ] 0
|
||||
@@ -402,20 +412,22 @@ OI Other_GETX [0 ] 0
|
||||
OI Other_GETS [0 ] 0
|
||||
OI Merged_GETS [0 ] 0
|
||||
OI Other_GETS_No_Mig [0 ] 0
|
||||
OI NC_DMA_GETS [0 ] 0
|
||||
OI Invalidate [0 ] 0
|
||||
OI Writeback_Ack [0 ] 0
|
||||
|
||||
MI Load [0 ] 0
|
||||
MI Ifetch [36 ] 36
|
||||
MI Store [5 ] 5
|
||||
MI Ifetch [1 ] 1
|
||||
MI Store [0 ] 0
|
||||
MI L2_Replacement [0 ] 0
|
||||
MI L1_to_L2 [0 ] 0
|
||||
MI Other_GETX [0 ] 0
|
||||
MI Other_GETS [0 ] 0
|
||||
MI Merged_GETS [0 ] 0
|
||||
MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [848 ] 848
|
||||
MI Writeback_Ack [852 ] 852
|
||||
|
||||
II Load [0 ] 0
|
||||
II Ifetch [0 ] 0
|
||||
@@ -425,6 +437,7 @@ II L1_to_L2 [0 ] 0
|
||||
II Other_GETX [0 ] 0
|
||||
II Other_GETS [0 ] 0
|
||||
II Other_GETS_No_Mig [0 ] 0
|
||||
II NC_DMA_GETS [0 ] 0
|
||||
II Invalidate [0 ] 0
|
||||
II Writeback_Ack [0 ] 0
|
||||
II Writeback_Nack [0 ] 0
|
||||
@@ -439,6 +452,7 @@ IT Other_GETX [0 ] 0
|
||||
IT Other_GETS [0 ] 0
|
||||
IT Merged_GETS [0 ] 0
|
||||
IT Other_GETS_No_Mig [0 ] 0
|
||||
IT NC_DMA_GETS [0 ] 0
|
||||
IT Invalidate [0 ] 0
|
||||
|
||||
ST Load [0 ] 0
|
||||
@@ -451,6 +465,7 @@ ST Other_GETX [0 ] 0
|
||||
ST Other_GETS [0 ] 0
|
||||
ST Merged_GETS [0 ] 0
|
||||
ST Other_GETS_No_Mig [0 ] 0
|
||||
ST NC_DMA_GETS [0 ] 0
|
||||
ST Invalidate [0 ] 0
|
||||
|
||||
OT Load [0 ] 0
|
||||
@@ -463,30 +478,33 @@ OT Other_GETX [0 ] 0
|
||||
OT Other_GETS [0 ] 0
|
||||
OT Merged_GETS [0 ] 0
|
||||
OT Other_GETS_No_Mig [0 ] 0
|
||||
OT NC_DMA_GETS [0 ] 0
|
||||
OT Invalidate [0 ] 0
|
||||
|
||||
MT Load [0 ] 0
|
||||
MT Ifetch [0 ] 0
|
||||
MT Store [10 ] 10
|
||||
MT Store [2 ] 2
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L1_to_L2 [154 ] 154
|
||||
MT Complete_L2_to_L1 [1 ] 1
|
||||
MT L1_to_L2 [39 ] 39
|
||||
MT Complete_L2_to_L1 [9 ] 9
|
||||
MT Other_GETX [0 ] 0
|
||||
MT Other_GETS [0 ] 0
|
||||
MT Merged_GETS [0 ] 0
|
||||
MT Other_GETS_No_Mig [0 ] 0
|
||||
MT NC_DMA_GETS [0 ] 0
|
||||
MT Invalidate [0 ] 0
|
||||
|
||||
MMT Load [0 ] 0
|
||||
MMT Ifetch [11 ] 11
|
||||
MMT Store [41 ] 41
|
||||
MMT Ifetch [0 ] 0
|
||||
MMT Store [21 ] 21
|
||||
MMT L2_Replacement [0 ] 0
|
||||
MMT L1_to_L2 [586 ] 586
|
||||
MMT Complete_L2_to_L1 [40 ] 40
|
||||
MMT L1_to_L2 [79 ] 79
|
||||
MMT Complete_L2_to_L1 [34 ] 34
|
||||
MMT Other_GETX [0 ] 0
|
||||
MMT Other_GETS [0 ] 0
|
||||
MMT Merged_GETS [0 ] 0
|
||||
MMT Other_GETS_No_Mig [0 ] 0
|
||||
MMT NC_DMA_GETS [0 ] 0
|
||||
MMT Invalidate [0 ] 0
|
||||
|
||||
Cache Stats: system.dir_cntrl0.probeFilter
|
||||
@@ -498,42 +516,42 @@ Cache Stats: system.dir_cntrl0.probeFilter
|
||||
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1616
|
||||
memory_reads: 856
|
||||
memory_writes: 760
|
||||
memory_refreshes: 446
|
||||
memory_total_request_delays: 1108
|
||||
memory_delays_per_request: 0.685644
|
||||
memory_delays_in_input_queue: 161
|
||||
memory_delays_behind_head_of_bank_queue: 2
|
||||
memory_delays_stalled_at_head_of_bank_queue: 945
|
||||
memory_stalls_for_bank_busy: 192
|
||||
memory_total_requests: 1626
|
||||
memory_reads: 859
|
||||
memory_writes: 767
|
||||
memory_refreshes: 440
|
||||
memory_total_request_delays: 1086
|
||||
memory_delays_per_request: 0.667897
|
||||
memory_delays_in_input_queue: 156
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 930
|
||||
memory_stalls_for_bank_busy: 238
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 83
|
||||
memory_stalls_for_bus: 395
|
||||
memory_stalls_for_arbitration: 61
|
||||
memory_stalls_for_bus: 358
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 154
|
||||
memory_stalls_for_read_read_turnaround: 121
|
||||
accesses_per_bank: 34 44 48 84 67 62 61 53 41 30 54 49 46 47 41 52 49 35 67 45 67 44 44 46 55 52 53 50 44 47 56 49
|
||||
memory_stalls_for_read_write_turnaround: 169
|
||||
memory_stalls_for_read_read_turnaround: 104
|
||||
accesses_per_bank: 41 42 40 76 63 66 54 43 49 56 52 46 53 60 61 57 50 44 44 42 48 49 42 47 53 52 49 52 50 47 41 57
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [770 ] 770
|
||||
GETS [91 ] 91
|
||||
PUT [909 ] 909
|
||||
GETX [767 ] 767
|
||||
GETS [93 ] 93
|
||||
PUT [907 ] 907
|
||||
Unblock [0 ] 0
|
||||
UnblockS [0 ] 0
|
||||
UnblockM [853 ] 853
|
||||
UnblockM [856 ] 856
|
||||
Writeback_Clean [0 ] 0
|
||||
Writeback_Dirty [0 ] 0
|
||||
Writeback_Exclusive_Clean [86 ] 86
|
||||
Writeback_Exclusive_Dirty [760 ] 760
|
||||
Writeback_Exclusive_Clean [85 ] 85
|
||||
Writeback_Exclusive_Dirty [767 ] 767
|
||||
Pf_Replacement [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [854 ] 854
|
||||
Memory_Ack [760 ] 760
|
||||
Memory_Data [859 ] 859
|
||||
Memory_Ack [767 ] 767
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
@@ -554,7 +572,7 @@ NX DMA_WRITE [0 ] 0
|
||||
|
||||
NO GETX [0 ] 0
|
||||
NO GETS [0 ] 0
|
||||
NO PUT [849 ] 849
|
||||
NO PUT [852 ] 852
|
||||
NO Pf_Replacement [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
@@ -573,8 +591,8 @@ O Pf_Replacement [0 ] 0
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
|
||||
E GETX [766 ] 766
|
||||
E GETS [90 ] 90
|
||||
E GETX [767 ] 767
|
||||
E GETS [92 ] 92
|
||||
E PUT [0 ] 0
|
||||
E DMA_READ [0 ] 0
|
||||
E DMA_WRITE [0 ] 0
|
||||
@@ -611,9 +629,9 @@ NO_R All_acks_and_data_no_sharers [0 ] 0
|
||||
|
||||
NO_B GETX [0 ] 0
|
||||
NO_B GETS [0 ] 0
|
||||
NO_B PUT [60 ] 60
|
||||
NO_B PUT [55 ] 55
|
||||
NO_B UnblockS [0 ] 0
|
||||
NO_B UnblockM [853 ] 853
|
||||
NO_B UnblockM [856 ] 856
|
||||
NO_B Pf_Replacement [0 ] 0
|
||||
NO_B DMA_READ [0 ] 0
|
||||
NO_B DMA_WRITE [0 ] 0
|
||||
@@ -624,6 +642,8 @@ NO_B_X PUT [0 ] 0
|
||||
NO_B_X UnblockS [0 ] 0
|
||||
NO_B_X UnblockM [0 ] 0
|
||||
NO_B_X Pf_Replacement [0 ] 0
|
||||
NO_B_X DMA_READ [0 ] 0
|
||||
NO_B_X DMA_WRITE [0 ] 0
|
||||
|
||||
NO_B_S GETX [0 ] 0
|
||||
NO_B_S GETS [0 ] 0
|
||||
@@ -647,6 +667,7 @@ O_B GETX [0 ] 0
|
||||
O_B GETS [0 ] 0
|
||||
O_B PUT [0 ] 0
|
||||
O_B UnblockS [0 ] 0
|
||||
O_B UnblockM [0 ] 0
|
||||
O_B Pf_Replacement [0 ] 0
|
||||
O_B DMA_READ [0 ] 0
|
||||
O_B DMA_WRITE [0 ] 0
|
||||
@@ -659,7 +680,7 @@ NO_B_W UnblockM [0 ] 0
|
||||
NO_B_W Pf_Replacement [0 ] 0
|
||||
NO_B_W DMA_READ [0 ] 0
|
||||
NO_B_W DMA_WRITE [0 ] 0
|
||||
NO_B_W Memory_Data [854 ] 854
|
||||
NO_B_W Memory_Data [859 ] 859
|
||||
|
||||
O_B_W GETX [0 ] 0
|
||||
O_B_W GETS [0 ] 0
|
||||
@@ -769,14 +790,14 @@ O_DR_B Shared_Ack [0 ] 0
|
||||
O_DR_B All_acks_and_owner_data [0 ] 0
|
||||
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
|
||||
WB GETX [2 ] 2
|
||||
WB GETS [1 ] 1
|
||||
WB GETX [0 ] 0
|
||||
WB GETS [0 ] 0
|
||||
WB PUT [0 ] 0
|
||||
WB Unblock [0 ] 0
|
||||
WB Writeback_Clean [0 ] 0
|
||||
WB Writeback_Dirty [0 ] 0
|
||||
WB Writeback_Exclusive_Clean [86 ] 86
|
||||
WB Writeback_Exclusive_Dirty [760 ] 760
|
||||
WB Writeback_Exclusive_Clean [85 ] 85
|
||||
WB Writeback_Exclusive_Dirty [767 ] 767
|
||||
WB Pf_Replacement [0 ] 0
|
||||
WB DMA_READ [0 ] 0
|
||||
WB DMA_WRITE [0 ] 0
|
||||
@@ -789,8 +810,8 @@ WB_O_W DMA_READ [0 ] 0
|
||||
WB_O_W DMA_WRITE [0 ] 0
|
||||
WB_O_W Memory_Ack [0 ] 0
|
||||
|
||||
WB_E_W GETX [2 ] 2
|
||||
WB_E_W GETS [0 ] 0
|
||||
WB_E_W GETX [0 ] 0
|
||||
WB_E_W GETS [1 ] 1
|
||||
WB_E_W PUT [0 ] 0
|
||||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
|
||||
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 14:43:33
|
||||
M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 5 2010 14:46:32
|
||||
M5 executing on svvint09
|
||||
M5 compiled Feb 8 2011 17:56:59
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:57:03
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 213851 because Ruby Tester completed
|
||||
Exiting @ tick 210961 because Ruby Tester completed
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 209796 # Number of bytes of host memory used
|
||||
host_seconds 0.44 # Real time elapsed on the host
|
||||
host_tick_rate 485996 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 212552 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_tick_rate 1803209 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000214 # Number of seconds simulated
|
||||
sim_ticks 213851 # Number of ticks simulated
|
||||
sim_seconds 0.000211 # Number of seconds simulated
|
||||
sim_ticks 210961 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
Reference in New Issue
Block a user