diff --git a/src/arch/arm/vtophys.cc b/src/arch/arm/vtophys.cc
index c915fa7f62..62f4d78f4c 100644
--- a/src/arch/arm/vtophys.cc
+++ b/src/arch/arm/vtophys.cc
@@ -54,12 +54,6 @@
 using namespace std;
 using namespace ArmISA;
 
-Addr
-ArmISA::vtophys(Addr vaddr)
-{
-    fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
-}
-
 static std::pair<bool, Addr>
 try_translate(ThreadContext *tc, Addr addr)
 {
@@ -97,7 +91,8 @@ ArmISA::vtophys(ThreadContext *tc, Addr addr)
     if (translation.first)
         return translation.second;
     else
-        panic("Table walkers support functional accesses. We should never get here\n");
+        panic("Table walkers support functional accesses. "
+                "We should never get here.");
 }
 
 bool
diff --git a/src/arch/arm/vtophys.hh b/src/arch/arm/vtophys.hh
index a72a24b7b9..7810b9885b 100644
--- a/src/arch/arm/vtophys.hh
+++ b/src/arch/arm/vtophys.hh
@@ -27,21 +27,23 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_ARM_VTOPHYS_H__
-#define __ARCH_ARM_VTOPHYS_H__
+#ifndef __ARCH_ARM_VTOPHYS_HH__
+#define __ARCH_ARM_VTOPHYS_HH__
 
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/utility.hh"
 
 class ThreadContext;
 
-namespace ArmISA {
-    inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
+namespace ArmISA
+{
 
-    Addr vtophys(Addr vaddr);
-    Addr vtophys(ThreadContext *tc, Addr vaddr);
-    bool virtvalid(ThreadContext *tc, Addr vaddr);
-}
+inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
 
-#endif // __ARCH_ARM_VTOPHYS_H__
+Addr vtophys(ThreadContext *tc, Addr vaddr);
+bool virtvalid(ThreadContext *tc, Addr vaddr);
+
+} // namespace ArmISA
+
+#endif // __ARCH_ARM_VTOPHYS_HH__
 
diff --git a/src/arch/mips/vtophys.cc b/src/arch/mips/vtophys.cc
index d37f5a1ea1..b4711fa339 100644
--- a/src/arch/mips/vtophys.cc
+++ b/src/arch/mips/vtophys.cc
@@ -29,22 +29,7 @@
 
 #include "arch/mips/vtophys.hh"
 
-#include <string>
-
-#include "base/chunk_generator.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-#include "debug/VtoPhys.hh"
-
-using namespace std;
-using namespace MipsISA;
-
-Addr
-MipsISA::vtophys(Addr vaddr)
-{
-    fatal("VTOPHYS: Unimplemented on MIPS\n");
-    return 0;
-}
+#include "base/logging.hh"
 
 Addr
 MipsISA::vtophys(ThreadContext *tc, Addr addr)
diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh
index 0f70c7701e..045d5baa76 100644
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@ -27,18 +27,20 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_MIPS_VTOPHYS_H__
-#define __ARCH_MIPS_VTOPHYS_H__
+#ifndef __ARCH_MIPS_VTOPHYS_HH__
+#define __ARCH_MIPS_VTOPHYS_HH__
 
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/utility.hh"
 
 class ThreadContext;
 
-namespace MipsISA {
-    Addr vtophys(Addr vaddr);
-    Addr vtophys(ThreadContext *tc, Addr vaddr);
+namespace MipsISA
+{
 
-};
-#endif // __ARCH_MIPS_VTOPHYS_H__
+Addr vtophys(ThreadContext *tc, Addr vaddr);
+
+} // namespace MipsISA
+
+#endif // __ARCH_MIPS_VTOPHYS_HH__
 
diff --git a/src/arch/power/vtophys.cc b/src/arch/power/vtophys.cc
index 9c57e41317..973facc318 100644
--- a/src/arch/power/vtophys.cc
+++ b/src/arch/power/vtophys.cc
@@ -30,12 +30,6 @@
 
 using namespace std;
 
-Addr
-PowerISA::vtophys(Addr vaddr)
-{
-    fatal("vtophys: Unimplemented on POWER\n");
-}
-
 Addr
 PowerISA::vtophys(ThreadContext *tc, Addr addr)
 {
diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh
index 2163494047..650fb5f1f0 100644
--- a/src/arch/power/vtophys.hh
+++ b/src/arch/power/vtophys.hh
@@ -36,9 +36,9 @@
 
 class ThreadContext;
 
-namespace PowerISA {
+namespace PowerISA
+{
 
-Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
 
 inline Addr
diff --git a/src/arch/riscv/vtophys.hh b/src/arch/riscv/vtophys.hh
index 29d9f4fd90..7dcc7af2d0 100644
--- a/src/arch/riscv/vtophys.hh
+++ b/src/arch/riscv/vtophys.hh
@@ -37,20 +37,13 @@
 
 class ThreadContext;
 
-namespace RiscvISA {
-
-inline Addr
-vtophys(Addr vaddr)
+namespace RiscvISA
 {
-    fatal("VTOPHYS: Unimplemented on RISC-V\n");
-    return vaddr;
-}
 
-inline Addr
+static inline Addr
 vtophys(ThreadContext *tc, Addr vaddr)
 {
     fatal("VTOPHYS: Unimplemented on RISC-V\n");
-    return vtophys(vaddr);
 }
 
 } // namespace RiscvISA
diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc
index 80727e68f2..906d082d03 100644
--- a/src/arch/sparc/vtophys.cc
+++ b/src/arch/sparc/vtophys.cc
@@ -30,6 +30,7 @@
 
 #include <string>
 
+#include "arch/sparc/pagetable.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/chunk_generator.hh"
 #include "base/compiler.hh"
@@ -40,20 +41,8 @@
 
 using namespace std;
 
-namespace SparcISA {
-
-Addr
-vtophys(Addr vaddr)
+namespace SparcISA
 {
-    // In SPARC it's almost always impossible to turn a VA->PA w/o a
-    // context The only times we can kinda do it are if we have a
-    // SegKPM mapping and can find the real address in the tlb or we
-    // have a physical adddress already (beacuse we are looking at the
-    // hypervisor) Either case is rare, so we'll just panic.
-
-    panic("vtophys() without context on SPARC largly worthless\n");
-    M5_DUMMY_RETURN;
-}
 
 Addr
 vtophys(ThreadContext *tc, Addr addr)
diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh
index c0d820fc52..33cefff2a8 100644
--- a/src/arch/sparc/vtophys.hh
+++ b/src/arch/sparc/vtophys.hh
@@ -26,19 +26,19 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_SPARC_VTOPHYS_H__
-#define __ARCH_SPARC_VTOPHYS_H__
+#ifndef __ARCH_SPARC_VTOPHYS_HH__
+#define __ARCH_SPARC_VTOPHYS_HH__
 
 #include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/pagetable.hh"
 
 class ThreadContext;
 
-namespace SparcISA {
+namespace SparcISA
+{
 
-Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
 
-};
-#endif // __ARCH_SPARC_VTOPHYS_H__
+}; // namespace SparcISA
+
+#endif // __ARCH_SPARC_VTOPHYS_HH__
 
diff --git a/src/arch/x86/vtophys.cc b/src/arch/x86/vtophys.cc
index ed025f82f5..5e07ddb3fb 100644
--- a/src/arch/x86/vtophys.cc
+++ b/src/arch/x86/vtophys.cc
@@ -47,27 +47,18 @@
 
 using namespace std;
 
-namespace X86ISA
+Addr
+X86ISA::vtophys(ThreadContext *tc, Addr vaddr)
 {
-    Addr
-    vtophys(Addr vaddr)
-    {
-        panic("Need access to page tables\n");
-    }
-
-    Addr
-    vtophys(ThreadContext *tc, Addr vaddr)
-    {
-        Walker *walker = dynamic_cast<TLB *>(tc->getDTBPtr())->getWalker();
-        unsigned logBytes;
-        Addr addr = vaddr;
-        Fault fault = walker->startFunctional(
-                tc, addr, logBytes, BaseTLB::Read);
-        if (fault != NoFault)
-            panic("vtophys page walk returned fault\n");
-        Addr masked_addr = vaddr & mask(logBytes);
-        Addr paddr = addr | masked_addr;
-        DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
-        return paddr;
-    }
+    Walker *walker = dynamic_cast<TLB *>(tc->getDTBPtr())->getWalker();
+    unsigned logBytes;
+    Addr addr = vaddr;
+    Fault fault = walker->startFunctional(
+            tc, addr, logBytes, BaseTLB::Read);
+    if (fault != NoFault)
+        panic("vtophys page walk returned fault\n");
+    Addr masked_addr = vaddr & mask(logBytes);
+    Addr paddr = addr | masked_addr;
+    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
+    return paddr;
 }
diff --git a/src/arch/x86/vtophys.hh b/src/arch/x86/vtophys.hh
index 93b423e19a..51ce8eb2e9 100644
--- a/src/arch/x86/vtophys.hh
+++ b/src/arch/x86/vtophys.hh
@@ -45,7 +45,6 @@ class ThreadContext;
 namespace X86ISA
 {
 
-Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
 
 }
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 736911a7e3..16fcc14dec 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -356,12 +356,6 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
    return fault;
 }
 
-Addr
-CheckerCPU::dbg_vtophys(Addr addr)
-{
-    return vtophys(tc, addr);
-}
-
 /**
  * Checks if the flags set by the Checker and Checkee match.
  */
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 763e3e9dfe..6bd702276f 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -135,8 +135,6 @@ class CheckerCPU : public BaseCPU, public ExecContext
     BaseTLB *itb;
     BaseTLB *dtb;
 
-    Addr dbg_vtophys(Addr addr);
-
     // ISAs like ARM can have multiple destination registers to check,
     // keep them all in a std::queue
     std::queue<InstResult> result;
diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index 6fd21f587a..e0ebef61f3 100644
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -143,15 +143,6 @@ MinorCPU::unserialize(CheckpointIn &cp)
     BaseCPU::unserialize(cp);
 }
 
-Addr
-MinorCPU::dbg_vtophys(Addr addr)
-{
-    /* Note that this gives you the translation for thread 0 */
-    panic("No implementation for vtophy\n");
-
-    return 0;
-}
-
 void
 MinorCPU::wakeup(ThreadID tid)
 {
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index c9dbb8fd99..b8ca087f5f 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -128,8 +128,6 @@ class MinorCPU : public BaseCPU
     void startup() override;
     void wakeup(ThreadID tid) override;
 
-    Addr dbg_vtophys(Addr addr);
-
     /** Processor-specific statistics */
     Minor::MinorStats stats;
 
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 6be7cc06d4..2f616f1ec1 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -422,12 +422,6 @@ change_thread_state(ThreadID tid, int activate, int priority)
 {
 }
 
-Addr
-BaseSimpleCPU::dbg_vtophys(Addr addr)
-{
-    return vtophys(threadContexts[curThread], addr);
-}
-
 void
 BaseSimpleCPU::wakeup(ThreadID tid)
 {
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index b270ff431d..df17c26725 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -121,9 +121,6 @@ class BaseSimpleCPU : public BaseCPU
     Status _status;
 
   public:
-    Addr dbg_vtophys(Addr addr);
-
-
     void checkForInterrupts();
     void setupFetchRequest(const RequestPtr &req);
     void preExecute();