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Merge vm1.(none):/home/stever/bk/newmem-head

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into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 1da75335907fee2d1745ec13e515819dfe2aad89
This commit is contained in:
Steve Reinhardt
2007-06-22 09:24:33 -07:00
parent bdd5fd20fb 470a6a9a74
commit 4d1bcbcd36
15 changed files with 334 additions and 242 deletions
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56
src/arch/micro_asm.py
View File

@@ -127,9 +127,13 @@ def print_error(message):
def handle_statement(parser, container, statement):
if statement.is_microop:
if statement.mnemonic not in parser.microops.keys():
raise Exception, "Unrecognized mnemonic: %s" % statement.mnemonic
parser.symbols["__microopClassFromInsideTheAssembler"] = \
parser.microops[statement.mnemonic]
try:
microop = eval('parser.microops[statement.mnemonic](%s)' %
statement.params)
microop = eval('__microopClassFromInsideTheAssembler(%s)' %
statement.params, {}, parser.symbols)
except:
print_error("Error creating microop object with mnemonic %s." % \
statement.mnemonic)
@@ -144,8 +148,13 @@ def handle_statement(parser, container, statement):
print_error("Error adding microop.")
raise
elif statement.is_directive:
if statement.name not in container.directives.keys():
raise Exception, "Unrecognized directive: %s" % statement.name
parser.symbols["__directiveFunctionFromInsideTheAssembler"] = \
container.directives[statement.name]
try:
eval('container.directives[statement.name](%s)' % statement.params)
eval('__directiveFunctionFromInsideTheAssembler(%s)' %
statement.params, {}, parser.symbols)
except:
print_error("Error executing directive.")
print container.directives
@@ -213,23 +222,6 @@ def t_params_COLON(t):
t.lexer.begin('asm')
return t
# An "ID" in the micro assembler is either a label, directive, or mnemonic
# If it's either a directive or a mnemonic, it will be optionally followed by
# parameters. If it's a label, the following colon will make the lexer stop
# looking for parameters.
def t_asm_ID(t):
r'[A-Za-z_]\w*'
t.type = reserved_map.get(t.value, 'ID')
t.lexer.begin('params')
return t
# If there is a label and you're -not- in the assember (which would be caught
# above), don't start looking for parameters.
def t_ANY_ID(t):
r'[A-Za-z_]\w*'
t.type = reserved_map.get(t.value, 'ID')
return t
# Parameters are a string of text which don't contain an unescaped statement
# statement terminator, ie a newline or semi colon.
def t_params_PARAMS(t):
@@ -243,6 +235,23 @@ def t_params_PARAMS(t):
t.lexer.begin('asm')
return t
# An "ID" in the micro assembler is either a label, directive, or mnemonic
# If it's either a directive or a mnemonic, it will be optionally followed by
# parameters. If it's a label, the following colon will make the lexer stop
# looking for parameters.
def t_asm_ID(t):
r'[A-Za-z_]\w*'
t.type = reserved_map.get(t.value, 'ID')
t.lexer.begin('params')
return t
# If there is a label and you're -not- in the assembler (which would be caught
# above), don't start looking for parameters.
def t_ANY_ID(t):
r'[A-Za-z_]\w*'
t.type = reserved_map.get(t.value, 'ID')
return t
# Braces enter and exit micro assembly
def t_INITIAL_LBRACE(t):
r'\{'
@@ -477,14 +486,11 @@ class MicroAssembler(object):
self.parser.microops = microops
self.parser.rom = rom
self.parser.rom_macroop_type = rom_macroop_type
self.parser.symbols = {}
self.symbols = self.parser.symbols
def assemble(self, asm):
self.parser.parse(asm, lexer=self.lexer)
# Begin debug printing
#for macroop in self.parser.macroops.values():
# print macroop
#print self.parser.rom
# End debug printing
macroops = self.parser.macroops
self.parser.macroops = {}
return macroops

2
src/arch/x86/intregs.hh
View File

@@ -150,4 +150,4 @@ namespace X86ISA
};
};
#endif // __ARCH_X86_INTERRUPTS_HH__
#endif // __ARCH_X86_INTREGS_HH__

5
src/arch/x86/isa/includes.isa
View File

@@ -97,7 +97,6 @@ output header {{
#include <iostream>
#include "arch/x86/emulenv.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/isa_traits.hh"
#include "arch/x86/regfile.hh"
#include "arch/x86/types.hh"
@@ -105,10 +104,12 @@ output header {{
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/request.hh" // some constructors use MemReq flags
#include "sim/faults.hh"
}};
output decoder {{
#include "arch/x86/faults.hh"
#include "arch/x86/segmentregs.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()

20
src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
View File

@@ -56,26 +56,22 @@
microcode = '''
def macroop SUB_R_I
{
subi "env.reg", "env.reg", "IMMEDIATE"
subi reg, reg, imm
};
def macroop SUB_M_I
{
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
subi "NUM_INTREGS+1", "NUM_INTREGS+1", "IMMEDIATE"
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
ld t1, ds, [scale, index, base], disp
subi t1, t1, imm
st t1, ds, [scale, index, base], disp
};
def macroop SUB_P_I
{
rdip "NUM_INTREGS+7"
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
subi "NUM_INTREGS+1", "NUM_INTREGS+1", "IMMEDIATE"
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
rdip t7
ld t1, ds, [scale, index, base], disp
subi t1, t1, imm
st t1, ds, [scale, index, base], disp
};
'''
#let {{

34
src/arch/x86/isa/insts/compare_and_test/test.py
View File

@@ -56,44 +56,40 @@
microcode = '''
def macroop TEST_M_R
{
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
and "NUM_INTREGS", "NUM_INTREGS+1", "env.reg"
ld t1, ds, [scale, index, base], disp
and t0, t1, reg
};
def macroop TEST_P_R
{
rdip "NUM_INTREGS+7"
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
and "NUM_INTREGS", "NUM_INTREGS+1", "env.reg"
rdip t7
ld t1, ds, [scale, index, base], disp
and t0, t1, reg
};
def macroop TEST_R_R
{
and "NUM_INTREGS", "env.reg", "env.regm"
and t0, reg, regm
};
def macroop TEST_M_I
{
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
limm "NUM_INTREGS+2", "IMMEDIATE"
and "NUM_INTREGS", "NUM_INTREGS+1", "NUM_INTREGS+2"
ld t1, ds, [scale, index, base], disp
limm t2, imm
and t0, t1, t2
};
def macroop TEST_P_I
{
rdip "NUM_INTREGS+7"
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
limm "NUM_INTREGS+2", "IMMEDIATE"
and "NUM_INTREGS", "NUM_INTREGS+1", "NUM_INTREGS+2"
rdip t7
ld t1, ds, [scale, index, base], disp
limm t2, imm
and t0, t1, t2
};
def macroop TEST_R_I
{
limm "NUM_INTREGS+1", "IMMEDIATE"
and "NUM_INTREGS", "env.reg", "NUM_INTREGS+1"
limm t1, imm
and t0, reg, t1
};
'''

13
src/arch/x86/isa/insts/control_transfer/call.py
View File

@@ -56,13 +56,14 @@
microcode = '''
def macroop CALL_I
{
.adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
limm "NUM_INTREGS+2", "IMMEDIATE"
rdip "NUM_INTREGS+1"
subi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
st "NUM_INTREGS+1", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
wrip "NUM_INTREGS+1", "NUM_INTREGS+2"
limm t2, imm
rdip t1
subi "INTREG_RSP", "INTREG_RSP", dsz
st t1, ss, [0, t0, "INTREG_RSP"]
wrip t1, t2
};
'''
#let {{

42
src/arch/x86/isa/insts/data_transfer/move.py
View File

@@ -55,59 +55,55 @@
microcode = '''
def macroop MOV_R_R {
mov "env.reg", "env.reg", "env.regm"
mov reg, reg, regm
};
def macroop MOV_M_R {
st "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
st reg, ds, [scale, index, base], disp
};
def macroop MOV_P_R {
rdip "NUM_INTREGS+7"
st "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
rdip t7
st reg, ds, [scale, index, base], disp
};
def macroop MOV_R_M {
ld "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
ld reg, ds, [scale, index, base], disp
};
def macroop MOV_R_P {
rdip "NUM_INTREGS+7"
ld "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
rdip t7
ld reg, ds, [scale, index, base], disp
};
def macroop MOV_R_I {
limm "env.reg", "IMMEDIATE"
limm reg, imm
};
def macroop MOV_M_I {
limm "NUM_INTREGS+1", "IMMEDIATE"
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
limm t1, imm
st t1, ds, [scale, index, base], disp
};
def macroop MOV_P_I {
rdip "NUM_INTREGS+7"
limm "NUM_INTREGS+1", "IMMEDIATE"
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
rdip t7
limm t1, imm
st t1, ds, [scale, index, base], disp
};
def macroop MOVSXD_R_R {
sext "env.reg", "env.regm", "env.dataSize"
sext reg, regm, dsz
};
def macroop MOVSXD_R_M {
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
sext "env.reg", "NUM_INTREGS+1", "env.dataSize"
ld t1, ds, [scale, index, base], disp
sext reg, t1, dsz
};
def macroop MOVSXD_R_P {
rdip "NUM_INTREGS+7"
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
sext "env.reg", "NUM_INTREGS+1", "env.dataSize"
rdip t7
ld t1, ds, [scale, index, base], disp
sext reg, t1, dsz
};
'''
#let {{

14
src/arch/x86/isa/insts/data_transfer/stack_operations.py
View File

@@ -55,21 +55,19 @@
microcode = '''
def macroop POP_R {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
.adjust_env oszIn64Override
ld "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
addi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
ld reg, ss, [0, t0, "INTREG_RSP"]
addi "INTREG_RSP", "INTREG_RSP", dsz
};
def macroop PUSH_R {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
.adjust_env oszIn64Override
subi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
st "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
subi "INTREG_RSP", "INTREG_RSP", dsz
st reg, ss, [0, t0, "INTREG_RSP"]
};
'''
#let {{

6
src/arch/x86/isa/insts/load_effective_address.py
View File

@@ -55,11 +55,11 @@
microcode = '''
def macroop LEA_R_M {
lea "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
lea reg, ds, [scale, index, base], disp
};
def macroop LEA_R_P {
rdip "NUM_INTREGS+7"
lea "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
rdip t7
lea reg, ds, [scale, index, base], disp
};
'''

62
src/arch/x86/isa/insts/logical.py
View File

@@ -56,74 +56,64 @@
microcode = '''
def macroop XOR_R_R
{
xor "env.reg", "env.reg", "env.regm"
xor reg, reg, regm
};
def macroop XOR_R_I
{
limm "NUM_INTREGS+1", "IMMEDIATE"
xor "env.reg", "env.reg", "NUM_INTREGS+1"
limm t1, imm
xor reg, reg, t1
};
def macroop XOR_M_R
{
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg"
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
ld t1, ds, [scale, index, base], disp
xor t1, t1, reg
st t1, ds, [scale, index, base], disp
};
def macroop XOR_P_R
{
rdip "NUM_INTREGS+7"
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg"
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
rdip t7
ld t1, ds, [scale, index, base], disp
xor t1, t1, reg
st t1, ds, [scale, index, base], disp
};
def macroop XOR_R_M
{
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
xor "env.reg", "env.reg", "NUM_INTREGS+1"
ld t1, ds, [scale, index, base], disp
xor reg, reg, t1
};
def macroop XOR_R_P
{
rdip "NUM_INTREGS+7"
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
xor "env.reg", "env.reg", "NUM_INTREGS+1"
rdip t7
ld t1, ds, [scale, index, base], disp
xor reg, reg, t1
};
def macroop AND_R_I
{
limm "NUM_INTREGS+1", "IMMEDIATE"
and "env.reg", "env.reg", "NUM_INTREGS+1"
limm t1, imm
and reg, reg, t1
};
def macroop AND_M_I
{
ld "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
limm "NUM_INTREGS+1", "IMMEDIATE"
and "NUM_INTREGS+2", "NUM_INTREGS+2", "NUM_INTREGS+1"
st "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
ld t2, ds, [scale, index, base], disp
limm t1, imm
and t2, t2, t1
st t2, ds, [scale, index, base], disp
};
def macroop AND_P_I
{
rdip "NUM_INTREGS+7"
ld "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
limm "NUM_INTREGS+1", "IMMEDIATE"
and "NUM_INTREGS+2", "NUM_INTREGS+2", "NUM_INTREGS+1"
st "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
"DISPLACEMENT"
rdip t7
ld t2, ds, [scale, index, base], disp
limm t1, imm
and t2, t2, t1
st t2, ds, [scale, index, base], disp
};
'''
#let {{

28
src/arch/x86/isa/microasm.isa
View File

@@ -72,5 +72,33 @@ let {{
from micro_asm import MicroAssembler, Rom_Macroop, Rom
mainRom = Rom('main ROM')
assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
# Add in symbols for the microcode registers
for num in range(15):
assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
# Add in symbols for the segment descriptor registers
for letter in ("C", "D", "E", "F", "G", "S"):
assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
# Miscellaneous symbols
symbols = {
"reg" : "env.reg",
"regm" : "env.regm",
"imm" : "IMMEDIATE",
"disp" : "DISPLACEMENT",
"scale" : "env.scale",
"index" : "env.index",
"base" : "env.base",
"dsz" : "env.dataSize",
"osz" : "env.operandSize",
"ssz" : "env.stackSize"
}
assembler.symbols.update(symbols)
# Code literal which forces a default 64 bit operand size in 64 bit mode.
assembler.symbols["oszIn64Override"] = '''
if (machInst.mode.submode == SixtyFourBitMode &&
env.dataSize == 4)
env.dataSize = 8;
'''
macroopDict = assembler.assemble(microcode)
}};

64
src/arch/x86/isa/microops/regop.isa
View File

@@ -162,6 +162,7 @@ def template MicroRegOpExecute {{
%(op_decl)s;
%(op_rd)s;
%(code)s;
%(flag_code)s;
//Write the resulting state to the execution context
if(fault == NoFault)
@@ -181,6 +182,7 @@ def template MicroRegOpImmExecute {{
%(op_decl)s;
%(op_rd)s;
%(code)s;
%(flag_code)s;
//Write the resulting state to the execution context
if(fault == NoFault)
@@ -304,11 +306,11 @@ def template MicroRegOpImmConstructor {{
let {{
class RegOp(X86Microop):
def __init__(self, dest, src1, src2):
def __init__(self, dest, src1, src2, setStatus):
self.dest = dest
self.src1 = src1
self.src2 = src2
self.setStatus = False
self.setStatus = setStatus
self.dataSize = "env.dataSize"
self.ext = 0
@@ -326,11 +328,11 @@ let {{
return allocator
class RegOpImm(X86Microop):
def __init__(self, dest, src1, imm8):
def __init__(self, dest, src1, imm8, setStatus):
self.dest = dest
self.src1 = src1
self.imm8 = imm8
self.setStatus = False
self.setStatus = setStatus
self.dataSize = "env.dataSize"
self.ext = 0
@@ -356,20 +358,22 @@ let {{
decoder_output = ""
exec_output = ""
def setUpMicroRegOp(name, Name, base, code, child):
def setUpMicroRegOp(name, Name, base, code, child, flagCode):
global header_output
global decoder_output
global exec_output
global microopClasses
iop = InstObjParams(name, Name, base, {"code" : code})
iop = InstObjParams(name, Name, base,
{"code" : code,
"flag_code" : flagCode})
header_output += MicroRegOpDeclare.subst(iop)
decoder_output += MicroRegOpConstructor.subst(iop)
exec_output += MicroRegOpExecute.subst(iop)
microopClasses[name] = child
def defineMicroRegOp(mnemonic, code):
def defineMicroRegOp(mnemonic, code, flagCode):
Name = mnemonic
name = mnemonic.lower()
@@ -382,31 +386,31 @@ let {{
# Build the all register version of this micro op
class RegOpChild(RegOp):
def __init__(self, dest, src1, src2):
super(RegOpChild, self).__init__(dest, src1, src2)
def __init__(self, dest, src1, src2, setStatus=False):
super(RegOpChild, self).__init__(dest, src1, src2, setStatus)
self.className = Name
self.mnemonic = name
setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild);
setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, flagCode);
# Build the immediate version of this micro op
class RegOpChildImm(RegOpImm):
def __init__(self, dest, src1, src2):
super(RegOpChildImm, self).__init__(dest, src1, src2)
def __init__(self, dest, src1, src2, setStatus=False):
super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus)
self.className = Name + "Imm"
self.mnemonic = name + "i"
setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm);
setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, flagCode);
defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF
defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF
defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF
defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF
defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg
defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)')
defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF
defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF
defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "")
defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF
defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "")
defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg
defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "")
# This has it's own function because Wr ops have implicit destinations
def defineMicroRegOpWr(mnemonic, code):
@@ -423,20 +427,20 @@ let {{
# Build the all register version of this micro op
class RegOpChild(RegOp):
def __init__(self, src1, src2):
super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2)
super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False)
self.className = Name
self.mnemonic = name
setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild);
setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, "");
# Build the immediate version of this micro op
class RegOpChildImm(RegOpImm):
def __init__(self, src1, src2):
super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2)
super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False)
self.className = Name + "Imm"
self.mnemonic = name + "i"
setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm);
setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, "");
defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')
@@ -447,11 +451,11 @@ let {{
class RegOpChild(RegOp):
def __init__(self, dest, src1 = "NUM_INTREGS"):
super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS")
super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
self.className = Name
self.mnemonic = name
setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild);
setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild, "");
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
@@ -461,11 +465,11 @@ let {{
class RegOpChild(RegOpImm):
def __init__(self, dest, src1, src2):
super(RegOpChild, self).__init__(dest, src1, src2)
super(RegOpChild, self).__init__(dest, src1, src2, False)
self.className = Name
self.mnemonic = name
setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild);
setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild, "");
defineMicroRegOpImm('Sext', '''
IntReg val = SrcReg1;

76
src/arch/x86/segmentregs.hh Normal file
View File

@@ -0,0 +1,76 @@
/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use of this software in source and binary forms,
* with or without modification, are permitted provided that the
* following conditions are met:
*
* The software must be used only for Non-Commercial Use which means any
* use which is NOT directed to receiving any direct monetary
* compensation for, or commercial advantage from such use. Illustrative
* examples of non-commercial use are academic research, personal study,
* teaching, education and corporate research & development.
* Illustrative examples of commercial use are distributing products for
* commercial advantage and providing services using the software for
* commercial advantage.
*
* If you wish to use this software or functionality therein that may be
* covered by patents for commercial use, please contact:
* Director of Intellectual Property Licensing
* Office of Strategy and Technology
* Hewlett-Packard Company
* 1501 Page Mill Road
* Palo Alto, California 94304
*
* Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. Redistributions
* in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution. Neither the name of
* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission. No right of
* sublicense is granted herewith. Derivatives of the software and
* output created using the software may be prepared, but only for
* Non-Commercial Uses. Derivatives of the software may be shared with
* others provided: (i) the others agree to abide by the list of
* conditions herein which includes the Non-Commercial Use restrictions;
* and (ii) such Derivatives of the software include the above copyright
* notice to acknowledge the contribution from this software where
* applicable, this list of conditions and the disclaimer below.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_SEGMENTREGS_HH__
#define __ARCH_X86_SEGMENTREGS_HH__
namespace X86ISA
{
enum SegmentRegIndex
{
SEGMENT_REG_ES,
SEGMENT_REG_CS,
SEGMENT_REG_SS,
SEGMENT_REG_DS,
SEGMENT_REG_FS,
SEGMENT_REG_GS,
NUM_SEGMENTREGS
};
};
#endif // __ARCH_X86_SEGMENTREGS_HH__