Merge ktlim@zizzer:/bk/m5

into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem SConstruct: src/SConscript: src/arch/SConscript: src/arch/alpha/faults.cc: src/arch/alpha/tlb.cc: src/base/traceflags.py: src/cpu/SConscript: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.cc: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/exec_context.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/regfile.hh: src/cpu/ozone/cpu.hh: src/cpu/simple/base.cc: src/cpu/base_dyn_inst.hh: src/cpu/o3/2bit_local_pred.cc: src/cpu/o3/2bit_local_pred.hh: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_dyn_inst.cc: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/bpred_unit.cc: src/cpu/o3/bpred_unit.hh: src/cpu/o3/bpred_unit_impl.hh: src/cpu/o3/btb.cc: src/cpu/o3/btb.hh: src/cpu/o3/comm.hh: src/cpu/o3/commit.cc: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu_policy.hh: src/cpu/o3/decode.cc: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.cc: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/free_list.cc: src/cpu/o3/free_list.hh: src/cpu/o3/iew.cc: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.cc: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/mem_dep_unit.hh: src/cpu/o3/mem_dep_unit_impl.hh: src/cpu/o3/ras.cc: src/cpu/o3/ras.hh: src/cpu/o3/rename.cc: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rename_map.cc: src/cpu/o3/rename_map.hh: src/cpu/o3/rob.cc: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/sat_counter.cc: src/cpu/o3/sat_counter.hh: src/cpu/o3/store_set.cc: src/cpu/o3/store_set.hh: src/cpu/o3/tournament_pred.cc: src/cpu/o3/tournament_pred.hh: Hand merges. --HG-- rename : build/SConstruct => SConstruct rename : SConscript => src/SConscript rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa rename : base/traceflags.py => src/base/traceflags.py rename : cpu/SConscript => src/cpu/SConscript rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh rename : cpu/cpu_models.py => src/cpu/cpu_models.py rename : cpu/exec_context.hh => src/cpu/exec_context.hh rename : cpu/exetrace.cc => src/cpu/exetrace.cc rename : cpu/exetrace.hh => src/cpu/exetrace.hh rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/static_inst.hh => src/cpu/static_inst.hh rename : kern/system_events.cc => src/kern/system_events.cc rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc extra : convert_revision : ff351fc0e3a7c0f23e59fdbec33d8209eb9280be
2006-05-30 14:17:41 -04:00
parent d308055afc f1fab2a446
commit 4a5b51b516
138 changed files with 32988 additions and 5311 deletions
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -26,29 +26,43 @@
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

-// Todo: Maybe have a special method for handling interrupts/traps.
-//
-// Traps:  Have IEW send a signal to commit saying that there's a trap to
-// be handled.  Have commit send the PC back to the fetch stage, along
-// with the current commit PC.  Fetch will directly access the IPR and save
-// off all the proper stuff.  Commit can send out a squash, or something
-// close to it.
-// Do the same for hwrei().  However, requires that commit be specifically
-// built to support that kind of stuff.  Probably not horrible to have
-// commit support having the CPU tell it to squash the other stages and
-// restart at a given address.  The IPR register does become an issue.
-// Probably not a big deal if the IPR stuff isn't cycle accurate.  Can just
-// have the original function handle writing to the IPR register.
-
-#ifndef __CPU_O3_CPU_SIMPLE_COMMIT_HH__
-#define __CPU_O3_CPU_SIMPLE_COMMIT_HH__
+#ifndef __CPU_O3_COMMIT_HH__
+#define __CPU_O3_COMMIT_HH__

+#include "arch/faults.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
+#include "cpu/exetrace.hh"
+#include "cpu/inst_seq.hh"
 #include "mem/memory_interface.hh"

+template <class>
+class O3ThreadState;
+
+/**
+ * DefaultCommit handles single threaded and SMT commit. Its width is
+ * specified by the parameters; each cycle it tries to commit that
+ * many instructions. The SMT policy decides which thread it tries to
+ * commit instructions from. Non- speculative instructions must reach
+ * the head of the ROB before they are ready to execute; once they
+ * reach the head, commit will broadcast the instruction's sequence
+ * number to the previous stages so that they can issue/ execute the
+ * instruction. Only one non-speculative instruction is handled per
+ * cycle. Commit is responsible for handling all back-end initiated
+ * redirects.  It receives the redirect, and then broadcasts it to all
+ * stages, indicating the sequence number they should squash until,
+ * and any necessary branch misprediction information as well. It
+ * priortizes redirects by instruction's age, only broadcasting a
+ * redirect if it corresponds to an instruction that should currently
+ * be in the ROB. This is done by tracking the sequence number of the
+ * youngest instruction in the ROB, which gets updated to any
+ * squashing instruction's sequence number, and only broadcasting a
+ * redirect if it corresponds to an older instruction. Commit also
+ * supports multiple cycle squashing, to model a ROB that can only
+ * remove a certain number of instructions per cycle.
+ */
 template<class Impl>
-class SimpleCommit
+class DefaultCommit
 {
  public:
    // Typedefs from the Impl.
@@ -57,62 +71,201 @@ class SimpleCommit
    typedef typename Impl::Params Params;
    typedef typename Impl::CPUPol CPUPol;

+    typedef typename CPUPol::RenameMap RenameMap;
    typedef typename CPUPol::ROB ROB;

    typedef typename CPUPol::TimeStruct TimeStruct;
+    typedef typename CPUPol::FetchStruct FetchStruct;
    typedef typename CPUPol::IEWStruct IEWStruct;
    typedef typename CPUPol::RenameStruct RenameStruct;

-  public:
-    // I don't believe commit can block, so it will only have two
-    // statuses for now.
-    // Actually if there's a cache access that needs to block (ie
-    // uncachable load or just a mem access in commit) then the stage
-    // may have to wait.
-    enum Status {
+    typedef typename CPUPol::Fetch Fetch;
+    typedef typename CPUPol::IEW IEW;
+
+    typedef O3ThreadState<Impl> Thread;
+
+    class TrapEvent : public Event {
+      private:
+        DefaultCommit<Impl> *commit;
+        unsigned tid;
+
+      public:
+        TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid);
+
+        void process();
+        const char *description();
+    };
+
+    /** Overall commit status. Used to determine if the CPU can deschedule
+     * itself due to a lack of activity.
+     */
+    enum CommitStatus{
+        Active,
+        Inactive
+    };
+
+    /** Individual thread status. */
+    enum ThreadStatus {
        Running,
        Idle,
        ROBSquashing,
-        DcacheMissStall,
-        DcacheMissComplete
+        TrapPending,
+        FetchTrapPending
+    };
+
+    /** Commit policy for SMT mode. */
+    enum CommitPolicy {
+        Aggressive,
+        RoundRobin,
+        OldestReady
    };

  private:
-    Status _status;
+    /** Overall commit status. */
+    CommitStatus _status;
+    /** Next commit status, to be set at the end of the cycle. */
+    CommitStatus _nextStatus;
+    /** Per-thread status. */
+    ThreadStatus commitStatus[Impl::MaxThreads];
+    /** Commit policy used in SMT mode. */
+    CommitPolicy commitPolicy;

  public:
-    SimpleCommit(Params &params);
+    /** Construct a DefaultCommit with the given parameters. */
+    DefaultCommit(Params *params);

+    /** Returns the name of the DefaultCommit. */
+    std::string name() const;
+
+    /** Registers statistics. */
    void regStats();

+    /** Sets the CPU pointer. */
    void setCPU(FullCPU *cpu_ptr);

+    /** Sets the list of threads. */
+    void setThreads(std::vector<Thread *> &threads);
+
+    /** Sets the main time buffer pointer, used for backwards communication. */
    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);

+    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
+
+    /** Sets the pointer to the queue coming from rename. */
    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);

+    /** Sets the pointer to the queue coming from IEW. */
    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);

+    void setFetchStage(Fetch *fetch_stage);
+
+    Fetch *fetchStage;
+
+    /** Sets the poitner to the IEW stage. */
+    void setIEWStage(IEW *iew_stage);
+
+    /** The pointer to the IEW stage. Used solely to ensure that
+     * various events (traps, interrupts, syscalls) do not occur until
+     * all stores have written back.
+     */
+    IEW *iewStage;
+
+    /** Sets pointer to list of active threads. */
+    void setActiveThreads(std::list<unsigned> *at_ptr);
+
+    /** Sets pointer to the commited state rename map. */
+    void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
+
+    /** Sets pointer to the ROB. */
    void setROB(ROB *rob_ptr);

+    /** Initializes stage by sending back the number of free entries. */
+    void initStage();
+
+    void switchOut();
+
+    void doSwitchOut();
+
+    void takeOverFrom();
+
+    /** Ticks the commit stage, which tries to commit instructions. */
    void tick();

+    /** Handles any squashes that are sent from IEW, and adds instructions
+     * to the ROB and tries to commit instructions.
+     */
    void commit();

-  private:
+    /** Returns the number of free ROB entries for a specific thread. */
+    unsigned numROBFreeEntries(unsigned tid);

+    void generateXCEvent(unsigned tid);
+
+  private:
+    /** Updates the overall status of commit with the nextStatus, and
+     * tell the CPU if commit is active/inactive. */
+    void updateStatus();
+
+    /** Sets the next status based on threads' statuses, which becomes the
+     * current status at the end of the cycle.
+     */
+    void setNextStatus();
+
+    /** Checks if the ROB is completed with squashing. This is for the case
+     * where the ROB can take multiple cycles to complete squashing.
+     */
+    bool robDoneSquashing();
+
+    /** Returns if any of the threads have the number of ROB entries changed
+     * on this cycle. Used to determine if the number of free ROB entries needs
+     * to be sent back to previous stages.
+     */
+    bool changedROBEntries();
+
+    void squashAll(unsigned tid);
+
+    void squashFromTrap(unsigned tid);
+
+    void squashFromXC(unsigned tid);
+
+    /** Commits as many instructions as possible. */
    void commitInsts();

+    /** Tries to commit the head ROB instruction passed in.
+     * @param head_inst The instruction to be committed.
+     */
    bool commitHead(DynInstPtr &head_inst, unsigned inst_num);

+    void generateTrapEvent(unsigned tid);
+
+    /** Gets instructions from rename and inserts them into the ROB. */
    void getInsts();

+    /** Marks completed instructions using information sent from IEW. */
    void markCompletedInsts();

-  public:
-    uint64_t readCommitPC();
+    /** Gets the thread to commit, based on the SMT policy. */
+    int getCommittingThread();

-    void setSquashing() { _status = ROBSquashing; }
+    /** Returns the thread ID to use based on a round robin policy. */
+    int roundRobin();
+
+    /** Returns the thread ID to use based on an oldest instruction policy. */
+    int oldestReady();
+
+  public:
+    /** Returns the PC of the head instruction of the ROB.
+     * @todo: Probably remove this function as it returns only thread 0.
+     */
+    uint64_t readPC() { return PC[0]; }
+
+    uint64_t readPC(unsigned tid) { return PC[tid]; }
+
+    void setPC(uint64_t val, unsigned tid) { PC[tid] = val; }
+
+    uint64_t readNextPC(unsigned tid) { return nextPC[tid]; }
+
+    void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }

  private:
    /** Time buffer interface. */
@@ -124,6 +277,10 @@ class SimpleCommit
    /** Wire to read information from IEW (for ROB). */
    typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;

+    TimeBuffer<FetchStruct> *fetchQueue;
+
+    typename TimeBuffer<FetchStruct>::wire fromFetch;
+
    /** IEW instruction queue interface. */
    TimeBuffer<IEWStruct> *iewQueue;

@@ -136,22 +293,56 @@ class SimpleCommit
    /** Wire to read information from rename queue. */
    typename TimeBuffer<RenameStruct>::wire fromRename;

+  public:
    /** ROB interface. */
    ROB *rob;

+  private:
    /** Pointer to FullCPU. */
    FullCPU *cpu;

    /** Memory interface.  Used for d-cache accesses. */
    MemInterface *dcacheInterface;

-  private:
+    std::vector<Thread *> thread;
+
+    Fault fetchFault;
+
+    int fetchTrapWait;
+
+    /** Records that commit has written to the time buffer this cycle. Used for
+     * the CPU to determine if it can deschedule itself if there is no activity.
+     */
+    bool wroteToTimeBuffer;
+
+    /** Records if the number of ROB entries has changed this cycle. If it has,
+     * then the number of free entries must be re-broadcast.
+     */
+    bool changedROBNumEntries[Impl::MaxThreads];
+
+    /** A counter of how many threads are currently squashing. */
+    int squashCounter;
+
+    /** Records if a thread has to squash this cycle due to a trap. */
+    bool trapSquash[Impl::MaxThreads];
+
+    /** Records if a thread has to squash this cycle due to an XC write. */
+    bool xcSquash[Impl::MaxThreads];
+
+    /** Priority List used for Commit Policy */
+    std::list<unsigned> priority_list;
+
    /** IEW to Commit delay, in ticks. */
    unsigned iewToCommitDelay;

+    /** Commit to IEW delay, in ticks. */
+    unsigned commitToIEWDelay;
+
    /** Rename to ROB delay, in ticks. */
    unsigned renameToROBDelay;

+    unsigned fetchToCommitDelay;
+
    /** Rename width, in instructions.  Used so ROB knows how many
     *  instructions to get from the rename instruction queue.
     */
@@ -165,16 +356,69 @@ class SimpleCommit
    /** Commit width, in instructions. */
    unsigned commitWidth;

-    Stats::Scalar<> commitCommittedInsts;
-    Stats::Scalar<> commitSquashedInsts;
-    Stats::Scalar<> commitSquashEvents;
-    Stats::Scalar<> commitNonSpecStalls;
-    Stats::Scalar<> commitCommittedBranches;
-    Stats::Scalar<> commitCommittedLoads;
-    Stats::Scalar<> commitCommittedMemRefs;
-    Stats::Scalar<> branchMispredicts;
+    /** Number of Reorder Buffers */
+    unsigned numRobs;

-    Stats::Distribution<> n_committed_dist;
+    /** Number of Active Threads */
+    unsigned numThreads;
+
+    bool switchPending;
+    bool switchedOut;
+
+    Tick trapLatency;
+
+    Tick fetchTrapLatency;
+
+    Tick fetchFaultTick;
+
+    Addr PC[Impl::MaxThreads];
+
+    Addr nextPC[Impl::MaxThreads];
+
+    /** The sequence number of the youngest valid instruction in the ROB. */
+    InstSeqNum youngestSeqNum[Impl::MaxThreads];
+
+    /** Pointer to the list of active threads. */
+    std::list<unsigned> *activeThreads;
+
+    /** Rename map interface. */
+    RenameMap *renameMap[Impl::MaxThreads];
+
+    void updateComInstStats(DynInstPtr &inst);
+
+    /** Stat for the total number of committed instructions. */
+    Stats::Scalar<> commitCommittedInsts;
+    /** Stat for the total number of squashed instructions discarded by commit.
+     */
+    Stats::Scalar<> commitSquashedInsts;
+    /** Stat for the total number of times commit is told to squash.
+     * @todo: Actually increment this stat.
+     */
+    Stats::Scalar<> commitSquashEvents;
+    /** Stat for the total number of times commit has had to stall due to a non-
+     * speculative instruction reaching the head of the ROB.
+     */
+    Stats::Scalar<> commitNonSpecStalls;
+    /** Stat for the total number of branch mispredicts that caused a squash. */
+    Stats::Scalar<> branchMispredicts;
+    /** Distribution of the number of committed instructions each cycle. */
+    Stats::Distribution<> numCommittedDist;
+
+    /** Total number of instructions committed. */
+    Stats::Vector<> statComInst;
+    /** Total number of software prefetches committed. */
+    Stats::Vector<> statComSwp;
+    /** Stat for the total number of committed memory references. */
+    Stats::Vector<> statComRefs;
+    /** Stat for the total number of committed loads. */
+    Stats::Vector<> statComLoads;
+    /** Total number of committed memory barriers. */
+    Stats::Vector<> statComMembars;
+    /** Total number of committed branches. */
+    Stats::Vector<> statComBranches;
+
+    Stats::Scalar<> commitEligibleSamples;
+    Stats::Vector<> commitEligible;
 };

-#endif // __CPU_O3_CPU_SIMPLE_COMMIT_HH__
+#endif // __CPU_O3_COMMIT_HH__