Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
SConstruct:
src/SConscript:
src/arch/SConscript:
src/arch/alpha/faults.cc:
src/arch/alpha/tlb.cc:
src/base/traceflags.py:
src/cpu/SConscript:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.cc:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/exec_context.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/regfile.hh:
src/cpu/ozone/cpu.hh:
src/cpu/simple/base.cc:
src/cpu/base_dyn_inst.hh:
src/cpu/o3/2bit_local_pred.cc:
src/cpu/o3/2bit_local_pred.hh:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_dyn_inst.cc:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/bpred_unit.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/btb.cc:
src/cpu/o3/btb.hh:
src/cpu/o3/comm.hh:
src/cpu/o3/commit.cc:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu_policy.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.cc:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/free_list.cc:
src/cpu/o3/free_list.hh:
src/cpu/o3/iew.cc:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/mem_dep_unit.hh:
src/cpu/o3/mem_dep_unit_impl.hh:
src/cpu/o3/ras.cc:
src/cpu/o3/ras.hh:
src/cpu/o3/rename.cc:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rename_map.cc:
src/cpu/o3/rename_map.hh:
src/cpu/o3/rob.cc:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/sat_counter.cc:
src/cpu/o3/sat_counter.hh:
src/cpu/o3/store_set.cc:
src/cpu/o3/store_set.hh:
src/cpu/o3/tournament_pred.cc:
src/cpu/o3/tournament_pred.hh:
Hand merges.
--HG--
rename : build/SConstruct => SConstruct
rename : SConscript => src/SConscript
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa
rename : base/traceflags.py => src/base/traceflags.py
rename : cpu/SConscript => src/cpu/SConscript
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc
rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh
rename : cpu/cpu_models.py => src/cpu/cpu_models.py
rename : cpu/exec_context.hh => src/cpu/exec_context.hh
rename : cpu/exetrace.cc => src/cpu/exetrace.cc
rename : cpu/exetrace.hh => src/cpu/exetrace.hh
rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh
rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc
rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh
rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc
rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh
rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh
rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh
rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh
rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc
rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh
rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh
rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc
rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh
rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh
rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc
rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh
rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh
rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc
rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh
rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh
rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc
rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc
rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh
rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc
rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc
rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh
rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh
rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc
rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh
rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh
rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh
rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh
rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc
rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/static_inst.hh => src/cpu/static_inst.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
extra : convert_revision : ff351fc0e3a7c0f23e59fdbec33d8209eb9280be
This commit is contained in:
Kevin Lim
8
python/m5/objects/FUPool.py
Normal file
8
python/m5/objects/FUPool.py
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@@ -0,0 +1,8 @@
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from m5 import *
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from FullCPU import OpType
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from FullCPU import OpDesc
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from FullCPU import FUDesc
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class FUPool(SimObject):
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type = 'FUPool'
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FUList = VectorParam.FUDesc("list of FU's for this pool")
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89
python/m5/objects/OzoneCPU.py
Normal file
89
python/m5/objects/OzoneCPU.py
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@@ -0,0 +1,89 @@
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from m5 import *
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from BaseCPU import BaseCPU
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class DerivOzoneCPU(BaseCPU):
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type = 'DerivOzoneCPU'
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numThreads = Param.Unsigned("number of HW thread contexts")
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if not build_env['FULL_SYSTEM']:
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mem = Param.FunctionalMemory(NULL, "memory")
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checker = Param.BaseCPU("Checker CPU")
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width = Param.Unsigned("Width")
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frontEndWidth = Param.Unsigned("Front end width")
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backEndWidth = Param.Unsigned("Back end width")
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backEndSquashLatency = Param.Unsigned("Back end squash latency")
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backEndLatency = Param.Unsigned("Back end latency")
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maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
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maxOutstandingMemOps = Param.Unsigned("Maximum number of outstanding memory operations")
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decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
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renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
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iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
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"delay")
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commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
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fetchWidth = Param.Unsigned("Fetch width")
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renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
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iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
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"delay")
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commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
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fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
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decodeWidth = Param.Unsigned("Decode width")
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iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
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"delay")
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commitToRenameDelay = Param.Unsigned("Commit to rename delay")
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decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
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renameWidth = Param.Unsigned("Rename width")
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commitToIEWDelay = Param.Unsigned("Commit to "
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"Issue/Execute/Writeback delay")
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renameToIEWDelay = Param.Unsigned("Rename to "
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"Issue/Execute/Writeback delay")
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issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
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"to the IEW stage)")
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issueWidth = Param.Unsigned("Issue width")
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executeWidth = Param.Unsigned("Execute width")
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executeIntWidth = Param.Unsigned("Integer execute width")
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executeFloatWidth = Param.Unsigned("Floating point execute width")
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executeBranchWidth = Param.Unsigned("Branch execute width")
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executeMemoryWidth = Param.Unsigned("Memory execute width")
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iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
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"delay")
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renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
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commitWidth = Param.Unsigned("Commit width")
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squashWidth = Param.Unsigned("Squash width")
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localPredictorSize = Param.Unsigned("Size of local predictor")
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localCtrBits = Param.Unsigned("Bits per counter")
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localHistoryTableSize = Param.Unsigned("Size of local history table")
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localHistoryBits = Param.Unsigned("Bits for the local history")
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globalPredictorSize = Param.Unsigned("Size of global predictor")
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globalCtrBits = Param.Unsigned("Bits per counter")
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globalHistoryBits = Param.Unsigned("Bits of history")
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choicePredictorSize = Param.Unsigned("Size of choice predictor")
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choiceCtrBits = Param.Unsigned("Bits of choice counters")
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BTBEntries = Param.Unsigned("Number of BTB entries")
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BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
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RASSize = Param.Unsigned("RAS size")
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LQEntries = Param.Unsigned("Number of load queue entries")
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SQEntries = Param.Unsigned("Number of store queue entries")
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LFSTSize = Param.Unsigned("Last fetched store table size")
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SSITSize = Param.Unsigned("Store set ID table size")
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numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
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numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
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"registers")
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numIQEntries = Param.Unsigned("Number of instruction queue entries")
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numROBEntries = Param.Unsigned("Number of reorder buffer entries")
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instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Cycle to start function trace")
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86
python/m5/objects/SimpleOzoneCPU.py
Normal file
86
python/m5/objects/SimpleOzoneCPU.py
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@@ -0,0 +1,86 @@
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from m5 import *
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from BaseCPU import BaseCPU
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class SimpleOzoneCPU(BaseCPU):
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type = 'SimpleOzoneCPU'
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numThreads = Param.Unsigned("number of HW thread contexts")
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if not build_env['FULL_SYSTEM']:
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mem = Param.FunctionalMemory(NULL, "memory")
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width = Param.Unsigned("Width")
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frontEndWidth = Param.Unsigned("Front end width")
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backEndWidth = Param.Unsigned("Back end width")
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backEndSquashLatency = Param.Unsigned("Back end squash latency")
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backEndLatency = Param.Unsigned("Back end latency")
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maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
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decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
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renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
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iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
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"delay")
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commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
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fetchWidth = Param.Unsigned("Fetch width")
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renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
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iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
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"delay")
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commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
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fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
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decodeWidth = Param.Unsigned("Decode width")
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iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
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"delay")
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commitToRenameDelay = Param.Unsigned("Commit to rename delay")
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decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
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renameWidth = Param.Unsigned("Rename width")
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commitToIEWDelay = Param.Unsigned("Commit to "
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"Issue/Execute/Writeback delay")
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renameToIEWDelay = Param.Unsigned("Rename to "
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"Issue/Execute/Writeback delay")
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issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
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"to the IEW stage)")
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issueWidth = Param.Unsigned("Issue width")
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executeWidth = Param.Unsigned("Execute width")
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executeIntWidth = Param.Unsigned("Integer execute width")
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executeFloatWidth = Param.Unsigned("Floating point execute width")
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executeBranchWidth = Param.Unsigned("Branch execute width")
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executeMemoryWidth = Param.Unsigned("Memory execute width")
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iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
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"delay")
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renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
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commitWidth = Param.Unsigned("Commit width")
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squashWidth = Param.Unsigned("Squash width")
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localPredictorSize = Param.Unsigned("Size of local predictor")
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localCtrBits = Param.Unsigned("Bits per counter")
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localHistoryTableSize = Param.Unsigned("Size of local history table")
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localHistoryBits = Param.Unsigned("Bits for the local history")
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globalPredictorSize = Param.Unsigned("Size of global predictor")
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globalCtrBits = Param.Unsigned("Bits per counter")
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globalHistoryBits = Param.Unsigned("Bits of history")
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choicePredictorSize = Param.Unsigned("Size of choice predictor")
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choiceCtrBits = Param.Unsigned("Bits of choice counters")
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BTBEntries = Param.Unsigned("Number of BTB entries")
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BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
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RASSize = Param.Unsigned("RAS size")
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LQEntries = Param.Unsigned("Number of load queue entries")
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SQEntries = Param.Unsigned("Number of store queue entries")
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LFSTSize = Param.Unsigned("Last fetched store table size")
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SSITSize = Param.Unsigned("Store set ID table size")
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numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
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numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
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"registers")
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numIQEntries = Param.Unsigned("Number of instruction queue entries")
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numROBEntries = Param.Unsigned("Number of reorder buffer entries")
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instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Cycle to start function trace")
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