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system-arm: Split the VExpress_GEM5_V1 base dts

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With the introduction of the new DPU model, we need different
variations of the VExpress_GEM5_V1 platform. This splits the platform
dtsi file into a separate file for the base platform and the
HDLCD-based platform. This matches the hierarchy in RealView.py.

Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11035
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Andreas Sandberg
2018-06-06 18:28:43 +01:00
parent 424048e55c
commit 4a37134f5f
6 changed files with 208 additions and 173 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
system/arm/dt/Makefile
View File

@@ -50,6 +50,8 @@ GEN_DTS=mkdir -p .gen; \
all: $(TARGETS)
platforms/vexpress_gem5_v1.dtsi: platforms/vexpress_gem5_v1_base.dtsi
.gen/armv7_gem5_v1_%cpu.dts: armv7.dts platforms/vexpress_gem5_v1.dtsi
$(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)

10
system/arm/dt/armv7.dts
View File

@@ -108,8 +108,8 @@
virt-encoder {
compatible = "drm,virtual-encoder";
port {
hdlcd0_virt_input: endpoint@0 {
remote-endpoint = <&hdlcd0_output>;
dp0_virt_input: endpoint@0 {
remote-endpoint = <&dp0_output>;
};
};
@@ -132,12 +132,12 @@
};
};
&hdlcd0 {
&dp0 {
status = "ok";
port {
hdlcd0_output: endpoint@0 {
remote-endpoint = <&hdlcd0_virt_input>;
dp0_output: endpoint@0 {
remote-endpoint = <&dp0_virt_input>;
};
};
};

10
system/arm/dt/armv8.dts
View File

@@ -112,8 +112,8 @@
virt-encoder {
compatible = "drm,virtual-encoder";
port {
hdlcd0_virt_input: endpoint@0 {
remote-endpoint = <&hdlcd0_output>;
dp0_virt_input: endpoint@0 {
remote-endpoint = <&dp0_output>;
};
};
@@ -136,12 +136,12 @@
};
};
&hdlcd0 {
&dp0 {
status = "ok";
port {
hdlcd0_output: endpoint@0 {
remote-endpoint = <&hdlcd0_virt_input>;
dp0_output: endpoint@0 {
remote-endpoint = <&dp0_virt_input>;
};
};
};

10
system/arm/dt/armv8_big_little.dts
View File

@@ -110,8 +110,8 @@
virt-encoder {
compatible = "drm,virtual-encoder";
port {
hdlcd0_virt_input: endpoint@0 {
remote-endpoint = <&hdlcd0_output>;
dp0_virt_input: endpoint@0 {
remote-endpoint = <&dp0_output>;
};
};
@@ -134,12 +134,12 @@
};
};
&hdlcd0 {
&dp0 {
status = "ok";
port {
hdlcd0_output: endpoint@0 {
remote-endpoint = <&hdlcd0_virt_input>;
dp0_output: endpoint@0 {
remote-endpoint = <&dp0_virt_input>;
};
};
};

165
system/arm/dt/platforms/vexpress_gem5_v1.dtsi
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017 ARM Limited
* Copyright (c) 2015-2018 ARM Limited
* All rights reserved
*
* Redistribution and use in source and binary forms, with or without
@@ -28,62 +28,14 @@
* Authors: Andreas Sandberg
*/
#include "vexpress_gem5_v1_base.dtsi"
/ {
arm,hbi = <0x0>;
arm,vexpress,site = <0xf>;
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
gic: interrupt-controller@2c001000 {
compatible = "gem5,gic", "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x2c001000 0 0x1000>,
<0 0x2c002000 0 0x1000>,
<0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
timer {
compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>;
clocks = <&osc_sys>;
clock-names="apb_pclk";
};
pci {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#address-cells = <0x3>;
#size-cells = <0x2>;
#interrupt-cells = <0x1>;
reg = <0x0 0x30000000 0x0 0x10000000>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>,
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>,
<0x000800 0x0 0x0 0 &gic 0 69 1>,
<0x001000 0x0 0x0 0 &gic 0 70 1>,
<0x001800 0x0 0x0 0 &gic 0 71 1>;
interrupt-map-mask = <0x001800 0x0 0x0 0x0>;
dma-coherent;
};
/* Ths HDLCD controller driver hasn't reached mainline
* yet. Disable it by default in the platform until the DT
* bindings have stabilize.
/* The display processor needs custom configuration to setup its
* output ports. Disable it by default in the platform until the
* DT bindings have stabilize.
*/
hdlcd0: hdlcd@2b000000 {
dp0: hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0x0 0x2b000000 0x0 0x1000>;
interrupts = <0 63 4>;
@@ -92,107 +44,4 @@
status = "disabled";
};
kmi@1c060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x1c060000 0x0 0x1000>;
interrupts = <0 12 4>;
clocks = <&v2m_clk24mhz>, <&osc_smb>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@1c070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x1c070000 0x0 0x1000>;
interrupts = <0 13 4>;
clocks = <&v2m_clk24mhz>, <&osc_smb>;
clock-names = "KMIREFCLK", "apb_pclk";
};
uart0: uart@1c090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x1c090000 0x0 0x1000>;
interrupts = <0 5 4>;
clocks = <&osc_peripheral>, <&osc_smb>;
clock-names = "uartclk", "apb_pclk";
};
rtc@1c170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x1c170000 0x0 0x1000>;
interrupts = <0 4 4>;
clocks = <&osc_smb>;
clock-names = "apb_pclk";
};
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_sysreg: sysreg@1c010000 {
compatible = "arm,vexpress-sysreg";
reg = <0 0x1c010000 0x0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};
vio@1c130000 {
compatible = "virtio,mmio";
reg = <0 0x1c130000 0x0 0x1000>;
interrupts = <0 42 4>;
};
vio@1c140000 {
compatible = "virtio,mmio";
reg = <0 0x1c140000 0x0 0x1000>;
interrupts = <0 43 4>;
};
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
osc_pxl: osc@5 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
freq-range = <23750000 1000000000>;
#clock-cells = <0>;
clock-output-names = "oscclk5";
};
osc_smb: osc@6 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 6>;
freq-range = <20000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk6";
};
osc_sys: osc@7 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 7>;
freq-range = <20000000 60000000>;
#clock-cells = <0>;
clock-output-names = "oscclk7";
};
};
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
arm,vexpress,site = <0>;
osc_peripheral: osc@2 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
freq-range = <24000000 24000000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk2";
};
};
};

184
system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi Normal file
View File

@@ -0,0 +1,184 @@
/*
* Copyright (c) 2015-2017 ARM Limited
* All rights reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Andreas Sandberg
*/
/ {
arm,hbi = <0x0>;
arm,vexpress,site = <0xf>;
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
gic: interrupt-controller@2c001000 {
compatible = "gem5,gic", "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x2c001000 0 0x1000>,
<0 0x2c002000 0 0x1000>,
<0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
timer {
compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>;
clocks = <&osc_sys>;
clock-names="apb_pclk";
};
pci {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#address-cells = <0x3>;
#size-cells = <0x2>;
#interrupt-cells = <0x1>;
reg = <0x0 0x30000000 0x0 0x10000000>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>,
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>,
<0x000800 0x0 0x0 0 &gic 0 69 1>,
<0x001000 0x0 0x0 0 &gic 0 70 1>,
<0x001800 0x0 0x0 0 &gic 0 71 1>;
interrupt-map-mask = <0x001800 0x0 0x0 0x0>;
dma-coherent;
};
kmi@1c060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x1c060000 0x0 0x1000>;
interrupts = <0 12 4>;
clocks = <&v2m_clk24mhz>, <&osc_smb>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@1c070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x1c070000 0x0 0x1000>;
interrupts = <0 13 4>;
clocks = <&v2m_clk24mhz>, <&osc_smb>;
clock-names = "KMIREFCLK", "apb_pclk";
};
uart0: uart@1c090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x1c090000 0x0 0x1000>;
interrupts = <0 5 4>;
clocks = <&osc_peripheral>, <&osc_smb>;
clock-names = "uartclk", "apb_pclk";
};
rtc@1c170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x1c170000 0x0 0x1000>;
interrupts = <0 4 4>;
clocks = <&osc_smb>;
clock-names = "apb_pclk";
};
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_sysreg: sysreg@1c010000 {
compatible = "arm,vexpress-sysreg";
reg = <0 0x1c010000 0x0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};
vio@1c130000 {
compatible = "virtio,mmio";
reg = <0 0x1c130000 0x0 0x1000>;
interrupts = <0 42 4>;
};
vio@1c140000 {
compatible = "virtio,mmio";
reg = <0 0x1c140000 0x0 0x1000>;
interrupts = <0 43 4>;
};
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
osc_pxl: osc@5 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
freq-range = <23750000 1000000000>;
#clock-cells = <0>;
clock-output-names = "oscclk5";
};
osc_smb: osc@6 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 6>;
freq-range = <20000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk6";
};
osc_sys: osc@7 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 7>;
freq-range = <20000000 60000000>;
#clock-cells = <0>;
clock-output-names = "oscclk7";
};
};
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
arm,vexpress,site = <0>;
osc_peripheral: osc@2 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
freq-range = <24000000 24000000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk2";
};
};
};