diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
index ab76d4cb5e..f731869f54 100644
--- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
+++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
@@ -25,16 +25,26 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from ......utils.override import overrides
-from ..abstract_dma_controller import AbstractDMAController
 
-from m5.objects import MessageBuffer
+from m5.objects import MessageBuffer, DMA_Controller
 
 
-class DMAController(AbstractDMAController):
-    def __init__(self, network, cache_line_size):
-        super().__init__(network, cache_line_size)
+class DMAController(DMA_Controller):
+    _version = 0
+
+    @classmethod
+    def _get_version(cls):
+        cls._version += 1
+        return cls._version - 1
+
+    def __init__(self, dma_sequencer, ruby_system):
+        super().__init__(
+            version=self._get_version(),
+            dma_sequencer=dma_sequencer,
+            ruby_system=ruby_system,
+        )
+        self.connectQueues(self.ruby_system.network)
 
-    @overrides(AbstractDMAController)
     def connectQueues(self, network):
         self.mandatoryQueue = MessageBuffer()
         self.responseFromDir = MessageBuffer(ordered=True)
diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
index 2ce13d3b08..9f47e411f8 100644
--- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
+++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
@@ -68,14 +68,14 @@ class L1Cache(L0Cache_Controller):
         self.Icache = RubyCache(
             size=l1i_size,
             assoc=l1i_assoc,
-            start_index_bit=self.getBlockSizeBits(),
+            start_index_bit=self.getBlockSizeBits(cache_line_size.value),
             is_icache=True,
             replacement_policy=LRURP(),
         )
         self.Dcache = RubyCache(
             size=l1d_size,
             assoc=l1d_assoc,
-            start_index_bit=self.getBlockSizeBits(),
+            start_index_bit=self.getBlockSizeBits(cache_line_size.value),
             is_icache=False,
             replacement_policy=LRURP(),
         )
@@ -88,12 +88,11 @@ class L1Cache(L0Cache_Controller):
         self.response_latency = 2
 
         self.version = self.versionCount()
-        self._cache_line_size = cache_line_size
         self.connectQueues(network)
 
-    def getBlockSizeBits(self):
-        bits = int(math.log(self._cache_line_size, 2))
-        if 2**bits != self._cache_line_size.value:
+    def getBlockSizeBits(self, cache_line_size):
+        bits = int(math.log(cache_line_size, 2))
+        if 2**bits != cache_line_size:
             raise Exception("Cache line size is not a power of 2!")
         return bits
 
diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
index e29f566191..d8c965924e 100644
--- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
+++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
@@ -67,7 +67,7 @@ class L2Cache(L1Cache_Controller):
         self.cache = RubyCache(
             size=l2_size,
             assoc=l2_assoc,
-            start_index_bit=self.getBlockSizeBits(),
+            start_index_bit=self.getBlockSizeBits(cache_line_size.value),
             is_icache=False,
         )
         # l2_select_num_bits is ruby backend terminology.
@@ -86,9 +86,14 @@ class L2Cache(L1Cache_Controller):
         self.to_l2_latency = 1
 
         self.version = self.versionCount()
-        self._cache_line_size = cache_line_size
         self.connectQueues(network)
 
+    def getBlockSizeBits(self, cache_line_size):
+        bits = int(math.log(cache_line_size, 2))
+        if 2**bits != cache_line_size:
+            raise Exception("Cache line size is not a power of 2!")
+        return bits
+
     def connectQueues(self, network):
         self.mandatoryQueue = MessageBuffer()
         self.optionalQueue = MessageBuffer()
diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py
index 6d46d1fdf0..0a93d9b0c8 100644
--- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py
+++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py
@@ -54,7 +54,7 @@ class L3Cache(L2Cache_Controller):
         self.L2cache = RubyCache(
             size=l3_size,
             assoc=l3_assoc,
-            start_index_bit=self.getIndexBit(num_l3Caches),
+            start_index_bit=self.getIndexBit(num_l3Caches, cache_line_size),
         )
 
         self.transitions_per_cycle = 4
@@ -64,12 +64,11 @@ class L3Cache(L2Cache_Controller):
         self.to_l1_latency = 1
 
         self.version = self.versionCount()
-        self._cache_line_size = cache_line_size
         self.connectQueues(network)
 
-    def getIndexBit(self, num_l3caches):
-        l3_bits = int(math.log(num_l3caches, 2))
-        bits = int(math.log(self._cache_line_size, 2)) + l3_bits
+    def getIndexBit(self, num_l3Caches, cache_line_size):
+        l3_bits = int(math.log(num_l3Caches, 2))
+        bits = int(math.log(cache_line_size, 2)) + l3_bits
         return bits
 
     def connectQueues(self, network):