diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 0a8479eb89..5f0fcc77a2 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -716,7 +716,7 @@ DRAMCtrl::processRespondEvent()
         accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
     }
 
-    delete respQueue.front();
+    assert(respQueue.front() == dram_pkt);
     respQueue.pop_front();
 
     if (!respQueue.empty()) {
@@ -738,6 +738,8 @@ DRAMCtrl::processRespondEvent()
         }
     }
 
+    delete dram_pkt;
+
     // We have made a location in the queue available at this point,
     // so if there is a read that was forced to wait, retry now
     if (retryRdReq) {