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dev-amdgpu: Fix issues with PM4 queue map, fences

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The PM4 release_mem packet is used as a DMA fence in the driver. It
specifies which queue the interrupt came from by encoding the me, pipe,
and queue fields from the map_queue packet into the interrupt ring ID.
Currently these fields are incorrect because (1) the order in the
bitfield is backwards, (2) the queue constructor assigns a pointer to
the PM4MapQueue packet containing this data to the dmaBuffer which gets
deleted in short order, and (3) the order of the encoding of ring ID is
incorrect.

This change fixes these issues by (1) placing the struct vales in
correct order, (2) creating a const copy of the dmaBuffer on
construction, and (3) using the ring ID encoding expected by the driver:
https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/
     drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c#L5989

Change-Id: I72c382980e57573f8a8a6879912c4139c7e2f505
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65095
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Matthew Poremba
2022-10-30 12:41:47 -07:00
parent c5feca8251
commit 489074fbfd
4 changed files with 26 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
src/dev/amdgpu/pm4_packet_processor.cc
View File

@@ -116,14 +116,14 @@ void
PM4PacketProcessor::mapKiq(Addr offset)
{
DPRINTF(PM4PacketProcessor, "Mapping KIQ\n");
newQueue((QueueDesc *)&kiq, offset);
newQueue((QueueDesc *)&kiq, offset, &kiq_pkt);
}
void
PM4PacketProcessor::mapPq(Addr offset)
{
DPRINTF(PM4PacketProcessor, "Mapping PQ\n");
newQueue((QueueDesc *)&pq, offset);
newQueue((QueueDesc *)&pq, offset, &pq_pkt);
}
void
@@ -146,8 +146,9 @@ PM4PacketProcessor::newQueue(QueueDesc *mqd, Addr offset,
: QueueType::Compute;
gpuDevice->setDoorbellType(offset, qt);
DPRINTF(PM4PacketProcessor, "New PM4 queue %d, base: %p offset: %p\n",
id, q->base(), q->offset());
DPRINTF(PM4PacketProcessor, "New PM4 queue %d, base: %p offset: %p, me: "
"%d, pipe %d queue: %d\n", id, q->base(), q->offset(), q->me(),
q->pipe(), q->queue());
}
void
@@ -490,14 +491,16 @@ PM4PacketProcessor::releaseMemDone(PM4Queue *q, PM4ReleaseMem *pkt, Addr addr)
DPRINTF(PM4PacketProcessor, "PM4 release_mem wrote %d to %p\n",
pkt->dataLo, addr);
if (pkt->intSelect == 2) {
DPRINTF(PM4PacketProcessor, "PM4 interrupt, ctx: %d, me: %d, pipe: "
"%d, queueSlot:%d\n", pkt->intCtxId, q->me(), q->pipe(),
q->queue());
// Rearranging the queue field of PM4MapQueues as the interrupt RingId
// format specified in PM4ReleaseMem pkt.
uint32_t ringId = (q->me() << 6) | (q->pipe() << 4) | q->queue();
DPRINTF(PM4PacketProcessor, "PM4 interrupt, id: %d ctx: %d, me: %d, "
"pipe: %d, queueSlot:%d\n", q->id(), pkt->intCtxId, q->me(),
q->pipe(), q->queue());
uint8_t ringId = 0;
if (q->id() != 0) {
ringId = (q->queue() << 4) | (q->me() << 2) | q->pipe();
}
gpuDevice->getIH()->prepareInterruptCookie(pkt->intCtxId, ringId,
SOC15_IH_CLIENTID_GRBM_CP, CP_EOP);
SOC15_IH_CLIENTID_GRBM_CP, CP_EOP);
gpuDevice->getIH()->submitInterruptCookie();
}