arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.

src/cpu/base.cc

@@ -126,6 +126,8 @@ BaseCPU::BaseCPU(Params *p, bool is_checker)
       _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
       interrupts(p->interrupts), profileEvent(NULL),
       numThreads(p->numThreads), system(p->system),
+      functionTraceStream(nullptr), currentFunctionStart(0),
+      currentFunctionEnd(0), functionEntryTick(0),
       addressMonitor()
 {
     // if Python did not provide a valid ID, do it here

src/cpu/minor/decode.cc

@@ -60,7 +60,8 @@ Decode::Decode(const std::string &name,
     inputBuffer(name + ".inputBuffer", "insts", params.decodeInputBufferSize),
     inputIndex(0),
     inMacroop(false),
-    execSeqNum(InstId::firstExecSeqNum)
+    execSeqNum(InstId::firstExecSeqNum),
+    blocked(false)
 {
     if (outputWidth < 1)
         fatal("%s: executeInputWidth must be >= 1 (%d)\n", name, outputWidth);

src/cpu/minor/fetch1.hh

@@ -251,12 +251,6 @@ class Fetch1 : public Named
      *  prediction sequence numbers. */
     InstSeqNum predictionSeqNum;
 
-    /** The sequence number expected for the next returned cache line.  The
-     *  responses queue should be ordered and so, if the front of that queue
-     *  has a lower lineSeqNum than this, lines need to be discarded.  If it
-     *  has a higher lineSeqNum, our line hasn't appeared yet */
-    InstSeqNum expectedLineSeqNum;
-
     /** Blocked indication for report */
     bool blocked;
 

src/cpu/minor/fetch2.cc

@@ -76,7 +76,8 @@ Fetch2::Fetch2(const std::string &name,
     lastStreamSeqNum(InstId::firstStreamSeqNum),
     fetchSeqNum(InstId::firstFetchSeqNum),
     expectedStreamSeqNum(InstId::firstStreamSeqNum),
-    predictionSeqNum(InstId::firstPredictionSeqNum)
+    predictionSeqNum(InstId::firstPredictionSeqNum),
+    blocked(false)
 {
     if (outputWidth < 1)
         fatal("%s: decodeInputWidth must be >= 1 (%d)\n", name, outputWidth);

src/cpu/o3/lsq_unit.hh

@@ -280,8 +280,9 @@ class LSQUnit {
       public:
         /** Default constructor. */
         LSQSenderState()
-            : mainPkt(NULL), pendingPacket(NULL), outstanding(1),
-              noWB(false), isSplit(false), pktToSend(false), cacheBlocked(false)
+            : mainPkt(NULL), pendingPacket(NULL), idx(0), outstanding(1),
+              isLoad(false), noWB(false), isSplit(false),
+              pktToSend(false), cacheBlocked(false)
           { }
 
         /** Instruction who initiated the access to memory. */

src/cpu/o3/rename_map.cc

@@ -39,7 +39,7 @@ using namespace std;
 /**** SimpleRenameMap methods ****/
 
 SimpleRenameMap::SimpleRenameMap()
-    : freeList(NULL)
+    : freeList(NULL), zeroReg(0)
 {
 }
 

src/cpu/o3/rename_map.hh

@@ -172,7 +172,7 @@ class UnifiedRenameMap
     typedef SimpleRenameMap::RenameInfo RenameInfo;
 
     /** Default constructor.  init() must be called prior to use. */
-    UnifiedRenameMap() {};
+    UnifiedRenameMap() : regFile(nullptr) {};
 
     /** Destructor. */
     ~UnifiedRenameMap() {};

src/cpu/o3/thread_state.hh

@@ -90,7 +90,8 @@ struct O3ThreadState : public ThreadState {
 
     O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
         : ThreadState(_cpu, _thread_num, _process),
-          cpu(_cpu), noSquashFromTC(false), trapPending(false)
+          cpu(_cpu), noSquashFromTC(false), trapPending(false),
+          tc(nullptr)
     {
         if (!FullSystem)
             return;

src/cpu/simple/atomic.cc

@@ -110,7 +110,8 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
       drain_manager(NULL),
       icachePort(name() + ".icache_port", this),
       dcachePort(name() + ".dcache_port", this),
-      fastmem(p->fastmem)
+      fastmem(p->fastmem), dcache_access(false), dcache_latency(0),
+      ppCommit(nullptr)
 {
     _status = Idle;
 }

src/cpu/simple/base.cc

@@ -88,7 +88,8 @@ using namespace TheISA;
 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
     : BaseCPU(p),
       branchPred(p->branchPred),
-      traceData(NULL), thread(NULL)
+      traceData(NULL), thread(NULL), _status(Idle), interval_stats(false),
+      inst()
 {
     if (FullSystem)
         thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
@@ -266,18 +267,6 @@ BaseSimpleCPU::regStats()
         .prereq(dcacheStallCycles)
         ;
 
-    icacheRetryCycles
-        .name(name() + ".icache_retry_cycles")
-        .desc("ICache total retry cycles")
-        .prereq(icacheRetryCycles)
-        ;
-
-    dcacheRetryCycles
-        .name(name() + ".dcache_retry_cycles")
-        .desc("DCache total retry cycles")
-        .prereq(dcacheRetryCycles)
-        ;
-
     statExecutedInstType
         .init(Enums::Num_OpClass)
         .name(name() + ".op_class")

src/cpu/simple/base.hh

@@ -262,18 +262,10 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
     Stats::Scalar icacheStallCycles;
     Counter lastIcacheStall;
 
-    // number of cycles stalled for I-cache retries
-    Stats::Scalar icacheRetryCycles;
-    Counter lastIcacheRetry;
-
     // number of cycles stalled for D-cache responses
     Stats::Scalar dcacheStallCycles;
     Counter lastDcacheStall;
 
-    // number of cycles stalled for D-cache retries
-    Stats::Scalar dcacheRetryCycles;
-    Counter lastDcacheRetry;
-
     /// @{
     /// Total number of branches fetched
     Stats::Scalar numBranches;

src/cpu/simple_thread.cc

@@ -63,7 +63,8 @@ using namespace std;
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            Process *_process, TheISA::TLB *_itb,
                            TheISA::TLB *_dtb, TheISA::ISA *_isa)
-    : ThreadState(_cpu, _thread_num, _process), isa(_isa), system(_sys),
+    : ThreadState(_cpu, _thread_num, _process), isa(_isa),
+      predicate(false), system(_sys),
       itb(_itb), dtb(_dtb)
 {
     clearArchRegs();

src/cpu/static_inst.hh

@@ -247,7 +247,7 @@ class StaticInst : public RefCounted, public StaticInstFlags
     /// instruction.
     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
-          _numFPDestRegs(0), _numIntDestRegs(0),
+          _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0),
           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
     { }
 

src/cpu/thread_state.cc

@@ -43,8 +43,9 @@
 #include "sim/system.hh"
 
 ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
-    : numInst(0), numOp(0), numLoad(0), _status(ThreadContext::Halted),
-      baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
+    : numInst(0), numOp(0), numLoad(0), startNumLoad(0),
+      _status(ThreadContext::Halted), baseCpu(cpu),
+      _contextId(0), _threadId(_tid), lastActivate(0), lastSuspend(0),
       profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
       kernelStats(NULL), process(_process), physProxy(NULL), virtProxy(NULL),
       proxy(NULL), funcExeInst(0), storeCondFailures(0)