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arch-riscv: Add bootloader+kernel workload

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Aims to boot OpenSBI + Linux kernel.

Change-Id: I9ee93cc367e8c06bdd0c7ddf43335d32965be14d
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
This commit is contained in:
Hoa Nguyen
2023-10-04 00:56:48 -07:00
parent 85340973bf
commit 46a9d85215
4 changed files with 200 additions and 1 deletions
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4
src/arch/riscv/SConscript
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@@ -66,7 +66,9 @@ Source('bare_metal/fs_workload.cc', tags='riscv isa')
SimObject('PMAChecker.py', sim_objects=['PMAChecker'], tags='riscv isa')
SimObject('PMP.py', sim_objects=['PMP'], tags='riscv isa')
SimObject('RiscvDecoder.py', sim_objects=['RiscvDecoder'], tags='riscv isa')
SimObject('RiscvFsWorkload.py', sim_objects=['RiscvBareMetal', 'RiscvLinux'],
SimObject('RiscvFsWorkload.py',
sim_objects=['RiscvBareMetal', 'RiscvLinux',
'RiscvBootloaderKernelWorkload'],
tags='riscv isa')
SimObject('RiscvInterrupts.py', sim_objects=['RiscvInterrupts'],
tags='riscv isa')