derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

stdlib: Edit RiscvMatched RTC

Browse Source 
Fixed the bug that made FS mode break.
Changed RTC value as fix.

Change-Id: I0effa1ecd32a8a8845e619d940f8e0efe549cfc1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64013
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
paikunal
2022-09-30 14:37:11 -07:00
committed by Kunal Pai
parent 9a1074d27f
commit 4662e18981
1 changed files with 1 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
View File

@@ -104,8 +104,6 @@ class RISCVMatchedBoard(
Details can be found on page 77, section 7.1 of the datasheet.
Datasheet for inbuilt params can be found here: https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
NOTE: FS Mode does not work yet.
"""
def __init__(
@@ -153,7 +151,7 @@ class RISCVMatchedBoard(
# Add the RTC
self.platform.rtc = RiscvRTC(
frequency=Frequency("1MHz")
frequency=Frequency("100MHz")
) # page 77, section 7.1
self.platform.clint.int_pin = self.platform.rtc.int_pin