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--HG--
extra : convert_revision : f677debfd636d79bc5097eb45331601d3253743d
This commit is contained in:
Gabe Black
2007-08-01 15:54:25 -07:00
parent c032a535ab 84cd78e96f
commit 458dfc8b3e
20 changed files with 130 additions and 224 deletions
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2
src/arch/alpha/SConscript
View File

@@ -38,12 +38,12 @@ if env['TARGET_ISA'] == 'alpha':
Source('miscregfile.cc')
Source('regfile.cc')
Source('remote_gdb.cc')
Source('utility.cc')
if env['FULL_SYSTEM']:
SimObject('AlphaSystem.py')
SimObject('AlphaTLB.py')
Source('arguments.cc')
Source('ev5.cc')
Source('idle_event.cc')
Source('ipr.cc')

150
src/arch/alpha/arguments.hh
View File

@@ -1,150 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
*/
#ifndef __ARCH_ALPHA_ARGUMENTS_HH__
#define __ARCH_ALPHA_ARGUMENTS_HH__
#include <assert.h>
#include "arch/alpha/vtophys.hh"
#include "base/refcnt.hh"
#include "mem/vport.hh"
#include "sim/host.hh"
class ThreadContext;
namespace AlphaISA {
class Arguments
{
protected:
ThreadContext *tc;
int number;
uint64_t getArg(bool fp = false);
protected:
class Data : public RefCounted
{
public:
Data(){}
~Data();
private:
std::list<char *> data;
public:
char *alloc(size_t size);
};
RefCountingPtr<Data> data;
public:
Arguments(ThreadContext *ctx, int n = 0)
: tc(ctx), number(n), data(NULL)
{ assert(number >= 0); data = new Data;}
Arguments(const Arguments &args)
: tc(args.tc), number(args.number), data(args.data) {}
~Arguments() {}
ThreadContext *getThreadContext() const { return tc; }
const Arguments &operator=(const Arguments &args) {
tc = args.tc;
number = args.number;
data = args.data;
return *this;
}
Arguments &operator++() {
++number;
assert(number >= 0);
return *this;
}
Arguments operator++(int) {
Arguments args = *this;
++number;
assert(number >= 0);
return args;
}
Arguments &operator--() {
--number;
assert(number >= 0);
return *this;
}
Arguments operator--(int) {
Arguments args = *this;
--number;
assert(number >= 0);
return args;
}
const Arguments &operator+=(int index) {
number += index;
assert(number >= 0);
return *this;
}
const Arguments &operator-=(int index) {
number -= index;
assert(number >= 0);
return *this;
}
Arguments operator[](int index) {
return Arguments(tc, index);
}
template <class T>
operator T() {
assert(sizeof(T) <= sizeof(uint64_t));
T data = static_cast<T>(getArg());
return data;
}
template <class T>
operator T *() {
T *buf = (T *)data->alloc(sizeof(T));
CopyData(tc, buf, getArg(), sizeof(T));
return buf;
}
operator char *() {
char *buf = data->alloc(2048);
CopyStringOut(tc, buf, getArg(), 2048);
return buf;
}
};
}; // namespace AlphaISA
#endif // __ARCH_ALPHA_ARGUMENTS_HH__

2
src/arch/alpha/linux/system.cc
View File

@@ -40,7 +40,6 @@
* up boot time.
*/
#include "arch/arguments.hh"
#include "arch/vtophys.hh"
#include "arch/alpha/idle_event.hh"
#include "arch/alpha/linux/system.hh"
@@ -54,6 +53,7 @@
#include "kern/linux/events.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "sim/arguments.hh"
#include "sim/byteswap.hh"
using namespace std;

45
src/arch/alpha/arguments.cc → src/arch/alpha/utility.cc
View File

@@ -26,45 +26,40 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Ali Saidi
*/
#include "arch/alpha/arguments.hh"
#include "arch/alpha/utility.hh"
#if FULL_SYSTEM
#include "arch/alpha/vtophys.hh"
#include "cpu/thread_context.hh"
#include "mem/vport.hh"
#endif
using namespace AlphaISA;
Arguments::Data::~Data()
namespace AlphaISA
{
while (!data.empty()) {
delete [] data.front();
data.pop_front();
}
}
char *
Arguments::Data::alloc(size_t size)
uint64_t getArgument(ThreadContext *tc, int number, bool fp)
{
char *buf = new char[size];
data.push_back(buf);
return buf;
}
uint64_t
Arguments::getArg(bool fp)
{
if (number < 6) {
#if FULL_SYSTEM
if (number < NumArgumentRegs) {
if (fp)
return tc->readFloatRegBits(16 + number);
return tc->readFloatRegBits(ArgumentReg[number]);
else
return tc->readIntReg(16 + number);
return tc->readIntReg(ArgumentReg[number]);
} else {
Addr sp = tc->readIntReg(30);
Addr sp = tc->readIntReg(StackPointerReg);
VirtualPort *vp = tc->getVirtPort(tc);
uint64_t arg = vp->read<uint64_t>(sp + (number-6) * sizeof(uint64_t));
uint64_t arg = vp->read<uint64_t>(sp +
(number-NumArgumentRegs) * sizeof(uint64_t));
tc->delVirtPort(vp);
return arg;
}
#else
panic("getArgument() is Full system only\n");
M5_DUMMY_RETURN
#endif
}
} // namespace AlphaISA

2
src/arch/alpha/utility.hh
View File

@@ -42,6 +42,8 @@
namespace AlphaISA
{
uint64_t getArgument(ThreadContext *tc, int number, bool fp);
static inline bool
inUserMode(ThreadContext *tc)
{

4
src/arch/mips/utility.hh
View File

@@ -48,6 +48,10 @@ class ThreadContext;
namespace MipsISA {
uint64_t getArgument(ThreadContext *tc, bool fp) {
panic("getArgument() not implemented for MIPS\n");
}
//Floating Point Utility Functions
uint64_t fpConvert(ConvertType cvt_type, double fp_val);
double roundFP(double val, int digits);

2
src/arch/sparc/SConscript
View File

@@ -39,12 +39,12 @@ if env['TARGET_ISA'] == 'sparc':
Source('miscregfile.cc')
Source('regfile.cc')
Source('remote_gdb.cc')
Source('utility.cc')
if env['FULL_SYSTEM']:
SimObject('SparcSystem.py')
SimObject('SparcTLB.py')
Source('arguments.cc')
Source('pagetable.cc')
Source('stacktrace.cc')
Source('system.cc')

149
src/arch/sparc/arguments.hh
View File

@@ -1,149 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
*/
#ifndef __ARCH_SPARC_ARGUMENTS_HH__
#define __ARCH_SPARC_ARGUMENTS_HH__
#include <assert.h>
#include "base/refcnt.hh"
#include "sim/host.hh"
#include "mem/vport.hh"
class ThreadContext;
namespace SparcISA {
class Arguments
{
protected:
ThreadContext *tc;
int number;
uint64_t getArg(bool fp = false);
protected:
class Data : public RefCounted
{
public:
Data(){}
~Data();
private:
std::list<char *> data;
public:
char *alloc(size_t size);
};
RefCountingPtr<Data> data;
public:
Arguments(ThreadContext *ctx, int n = 0)
: tc(ctx), number(n), data(NULL)
{ assert(number >= 0); data = new Data;}
Arguments(const Arguments &args)
: tc(args.tc), number(args.number), data(args.data) {}
~Arguments() {}
ThreadContext *getThreadContext() const { return tc; }
const Arguments &operator=(const Arguments &args) {
tc = args.tc;
number = args.number;
data = args.data;
return *this;
}
Arguments &operator++() {
++number;
assert(number >= 0);
return *this;
}
Arguments operator++(int) {
Arguments args = *this;
++number;
assert(number >= 0);
return args;
}
Arguments &operator--() {
--number;
assert(number >= 0);
return *this;
}
Arguments operator--(int) {
Arguments args = *this;
--number;
assert(number >= 0);
return args;
}
const Arguments &operator+=(int index) {
number += index;
assert(number >= 0);
return *this;
}
const Arguments &operator-=(int index) {
number -= index;
assert(number >= 0);
return *this;
}
Arguments operator[](int index) {
return Arguments(tc, index);
}
template <class T>
operator T() {
assert(sizeof(T) <= sizeof(uint64_t));
T data = static_cast<T>(getArg());
return data;
}
template <class T>
operator T *() {
T *buf = (T *)data->alloc(sizeof(T));
CopyData(tc, buf, getArg(), sizeof(T));
return buf;
}
operator char *() {
char *buf = data->alloc(2048);
CopyStringOut(tc, buf, getArg(), 2048);
return buf;
}
};
}; // namespace SparcISA
#endif // __ARCH_SPARC_ARGUMENTS_HH__

57
src/arch/sparc/arguments.cc → src/arch/sparc/utility.cc
View File

@@ -25,49 +25,40 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Authors: Gabe Black
* Ali Saidi
*/
#include "arch/sparc/arguments.hh"
#include "arch/sparc/utility.hh"
#if FULL_SYSTEM
#include "arch/sparc/vtophys.hh"
#include "cpu/thread_context.hh"
#include "mem/vport.hh"
#endif
using namespace SparcISA;
namespace SparcISA {
Arguments::Data::~Data()
{
while (!data.empty()) {
delete [] data.front();
data.pop_front();
}
}
char *
Arguments::Data::alloc(size_t size)
{
char *buf = new char[size];
data.push_back(buf);
return buf;
}
uint64_t
Arguments::getArg(bool fp)
{
//The caller uses %o0-%05 for the first 6 arguments even if their floating
//point. Double precision floating point values take two registers/args.
//Quads, structs, and unions are passed as pointers. All arguments beyond
//the sixth are passed on the stack past the 16 word window save area,
//space for the struct/union return pointer, and space reserved for the
//first 6 arguments which the caller may use but doesn't have to.
if (number < 6) {
return tc->readIntReg(8 + number);
//The caller uses %o0-%05 for the first 6 arguments even if their floating
//point. Double precision floating point values take two registers/args.
//Quads, structs, and unions are passed as pointers. All arguments beyond
//the sixth are passed on the stack past the 16 word window save area,
//space for the struct/union return pointer, and space reserved for the
//first 6 arguments which the caller may use but doesn't have to.
uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
#if FULL_SYSTEM
if (number < NumArgumentRegs) {
return tc->readIntReg(ArgumentReg[number]);
} else {
Addr sp = tc->readIntReg(14);
Addr sp = tc->readIntReg(StackPointerReg);
VirtualPort *vp = tc->getVirtPort(tc);
uint64_t arg = vp->read<uint64_t>(sp + 92 + (number-6) * sizeof(uint64_t));
uint64_t arg = vp->read<uint64_t>(sp + 92 +
(number-NumArgumentRegs) * sizeof(uint64_t));
tc->delVirtPort(vp);
return arg;
}
#else
panic("getArgument() only implemented for FULL_SYSTEM\n");
M5_DUMMY_RETURN
#endif
}
} //namespace SPARC_ISA

3
src/arch/sparc/utility.hh
View File

@@ -41,6 +41,9 @@
namespace SparcISA
{
uint64_t getArgument(ThreadContext *tc, int number, bool fp);
static inline bool
inUserMode(ThreadContext *tc)
{