From 457d97ea5256b4ef0080aaea32c3e0d3ac88db15 Mon Sep 17 00:00:00 2001
From: Matthew Poremba <matthew.poremba@amd.com>
Date: Fri, 15 Mar 2024 18:28:36 -0500
Subject: [PATCH] arch-vega: Implement V_XNOR_B32

Change-Id: Id23a8d984f227ca23a92adb6c7fde3b4627af054
---
 src/arch/amdgpu/vega/gpu_decoder.cc        |  3 +-
 src/arch/amdgpu/vega/insts/instructions.hh | 34 ++++++++++++++++++++++
 src/arch/amdgpu/vega/insts/vop2.cc         | 34 ++++++++++++++++++++++
 3 files changed, 69 insertions(+), 2 deletions(-)

diff --git a/src/arch/amdgpu/vega/gpu_decoder.cc b/src/arch/amdgpu/vega/gpu_decoder.cc
index 940840719b..a93b4c67da 100644
--- a/src/arch/amdgpu/vega/gpu_decoder.cc
+++ b/src/arch/amdgpu/vega/gpu_decoder.cc
@@ -4217,8 +4217,7 @@ namespace VegaISA
     GPUStaticInst*
     Decoder::decode_OP_VOP2__V_XNOR_B32(MachInst iFmt)
     {
-        fatal("Trying to decode instruction without a class\n");
-        return nullptr;
+        return new Inst_VOP2__V_XNOR_B32(&iFmt->iFmt_VOP2);
     }
 
     GPUStaticInst*
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh b/src/arch/amdgpu/vega/insts/instructions.hh
index db03548a3d..4151c2cb8b 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -8132,6 +8132,40 @@ namespace VegaISA
         void execute(GPUDynInstPtr) override;
     }; // Inst_VOP2__V_FMAC_F32
 
+    class Inst_VOP2__V_XNOR_B32 : public Inst_VOP2
+    {
+      public:
+        Inst_VOP2__V_XNOR_B32(InFmt_VOP2*);
+        ~Inst_VOP2__V_XNOR_B32();
+
+        int
+        getNumOperands() override
+        {
+            return numDstRegOperands() + numSrcRegOperands();
+        } // getNumOperands
+
+        int numDstRegOperands() override { return 1; }
+        int numSrcRegOperands() override { return 2; }
+
+        int
+        getOperandSize(int opIdx) override
+        {
+            switch (opIdx) {
+              case 0: //src_0
+                return 4;
+              case 1: //src_1
+                return 4;
+              case 2: //vdst
+                return 4;
+              default:
+                fatal("op idx %i out of bounds\n", opIdx);
+                return -1;
+            }
+        } // getOperandSize
+
+        void execute(GPUDynInstPtr) override;
+    }; // Inst_VOP2__V_XNOR_B32
+
     class Inst_VOP1__V_NOP : public Inst_VOP1
     {
       public:
diff --git a/src/arch/amdgpu/vega/insts/vop2.cc b/src/arch/amdgpu/vega/insts/vop2.cc
index 2672063d0c..55146711b6 100644
--- a/src/arch/amdgpu/vega/insts/vop2.cc
+++ b/src/arch/amdgpu/vega/insts/vop2.cc
@@ -2181,6 +2181,40 @@ namespace VegaISA
             }
         }
 
+        vdst.write();
+    } // execute
+    // --- Inst_VOP2__V_XNOR_B32 class methods ---
+
+    Inst_VOP2__V_XNOR_B32::Inst_VOP2__V_XNOR_B32(InFmt_VOP2 *iFmt)
+        : Inst_VOP2(iFmt, "v_xnor_b32")
+    {
+        setFlag(ALU);
+    } // Inst_VOP2__V_XNOR_B32
+
+    Inst_VOP2__V_XNOR_B32::~Inst_VOP2__V_XNOR_B32()
+    {
+    } // ~Inst_VOP2__V_XNOR_B32
+
+    // --- description from .arch file ---
+    // D.u = S1.u - S0.u;
+    void
+    Inst_VOP2__V_XNOR_B32::execute(GPUDynInstPtr gpuDynInst)
+    {
+        Wavefront *wf = gpuDynInst->wavefront();
+        ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+        ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+        VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+        src0.readSrc();
+        src1.read();
+        vdst.read();
+
+        for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+            if (wf->execMask(lane)) {
+                vdst[lane] = ~(src0[lane] ^ src1[lane]);
+            }
+        }
+
         vdst.write();
     } // execute
 } // namespace VegaISA