Have bus use the BadAddress device to handle bad addresses. The O3 CPU should be able to boot into Linux with caches on after this change.

src/mem/bus.cc:
src/mem/bus.hh:
    Bus now will be setup with a default responder, unless the user overrides it.  This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
    Bus now has a default responder for FS mode if the user doesn't override it.  It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
    Add bad address device.  Also record when the user has specified their own default responder.

--HG--
extra : convert_revision : 59070477ae313ee711b2d59baa2369c9a91c5b85

src/python/m5/objects/Tsunami.py

@@ -15,6 +15,9 @@ class IsaFake(BasicPioDevice):
     type = 'IsaFake'
     pio_size = Param.Addr(0x8, "Size of address range")
 
+class BadAddr(BasicPioDevice):
+    type = 'BadAddr'
+
 class TsunamiIO(BasicPioDevice):
     type = 'TsunamiIO'
     time = Param.UInt64(1136073600,
@@ -70,6 +73,7 @@ class Tsunami(Platform):
         self.cchip.pio = bus.port
         self.pchip.pio = bus.port
         self.pciconfig.pio = bus.default
+        bus.responder_set = True
         self.fake_sm_chip.pio = bus.port
         self.fake_uart1.pio = bus.port
         self.fake_uart2.pio = bus.port