arch-riscv: Fix Clint and SATP write side effects

Previously, RISC-V FS support was unable to support O3CPU.
It was due to two issues:

1. CLINT was calling tc->setMiscRegNoEffect which triggers
a conditionalSquash on O3CPU. These frequent squashes led
to assertion error in src/cpu/o3/inst_queue_impl.hh line
1293 (we still suspect that the assertion might contain
some assumptions).

2. A CSR write to SATP needs to trigger a squash (since
MMU can be activated). This is done by conditionally
adding the IsSquashAfter flag to CSR operations if the
target is SATP. This is a simple fix. (Else, an auipc
right after a CSR write to SATP might compute the wrong
value). In the future, a better implementation should
only set the flag for writes to the relevant bit(s).

Change-Id: Ieb9fd0b9aa09e4d2f270b28c2297ea821a81bf65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43244
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Peter Yuen <petery.hin@huawei.com>

src/dev/riscv/clint.cc

@@ -64,7 +64,9 @@ Clint::raiseInterruptPin(int id)
     for (int context_id = 0; context_id < nThread; context_id++) {
 
         // Update misc reg file
-        system->threads[context_id]->setMiscRegNoEffect(MISCREG_TIME, mtime);
+        ISA* isa = dynamic_cast<ISA*>(
+            system->threads[context_id]->getIsaPtr());
+        isa->setMiscRegNoEffect(MISCREG_TIME, mtime);
 
         // Post timer interrupt
         uint64_t mtimecmp = registers.mtimecmp[context_id].get();