configs, mem: Support running VIPER with GCN3

This changeset adds the necessary changes for running
GCN3 ISA with VIPER in apu_se.py.

Changes to the VIPER protocol configs are made to add support
for DMA and scalar caches.

hsaTopology is added to help the pseudo FS create the files
needed by ROCm to understand the device on which the SW is
being run.

Change-Id: I0f47a6a36bb241a26972c0faafafcf332a7d7d1f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30274
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/mem/request.hh

@@ -815,7 +815,6 @@ class Request
     bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
     bool isSecure() const { return _flags.isSet(SECURE); }
     bool isPTWalk() const { return _flags.isSet(PT_WALK); }
-    bool isAcquire() const { return _flags.isSet(ACQUIRE); }
     bool isRelease() const { return _flags.isSet(RELEASE); }
     bool isKernel() const { return _flags.isSet(KERNEL); }
     bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
@@ -839,6 +838,8 @@ class Request
     bool isToPOC() const { return _flags.isSet(DST_POC); }
     Flags getDest() const { return _flags & DST_BITS; }
 
+    bool isAcquire() const { return _cacheCoherenceFlags.isSet(ACQUIRE); }
+
     /**
      * Accessor functions for the memory space configuration flags and used by
      * GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that

src/mem/ruby/protocol/GPU_VIPER-SQC.sm

@@ -239,8 +239,6 @@ machine(MachineType:SQC, "GPU SQC (L1 I Cache)")
       peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
         Entry cache_entry := getCacheEntry(in_msg.LineAddress);
         TBE tbe := TBEs.lookup(in_msg.LineAddress);
-
-        assert(in_msg.Type == RubyRequestType:IFETCH);
         trigger(Event:Fetch, in_msg.LineAddress, cache_entry, tbe);
       }
     }