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configs, gpu-compute: update GPU scripts to remove master/slave

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Update apu_se and underlying configuration files for GPU runs to
replace the master/slave terminology.

Change-Id: Icf309782f0899dc412eccd27e3ac017902316a70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50967
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Matt Sinclair
2021-09-25 21:31:53 -05:00
parent a861b1d8d2
commit 43b8a93748
2 changed files with 34 additions and 28 deletions
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19
configs/common/GPUTLBConfig.py
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@@ -148,8 +148,8 @@ def config_tlb_hierarchy(options, system, shader_idx):
for TLB_type in hierarchy_level:
name = TLB_type['name']
for index in range(TLB_type['width']):
exec('system.%s_coalescer[%d].master[0] = \
system.%s_tlb[%d].slave[0]' % \
exec('system.%s_coalescer[%d].mem_side_ports[0] = \
system.%s_tlb[%d].cpu_side_ports[0]' % \
(name, index, name, index))
# Connect the cpuSidePort (slave) of all the coalescers in level 1
@@ -163,12 +163,12 @@ def config_tlb_hierarchy(options, system, shader_idx):
if tlb_per_cu:
for tlb in range(tlb_per_cu):
exec('system.cpu[%d].CUs[%d].translation_port[%d] = \
system.l1_coalescer[%d].slave[%d]' % \
system.l1_coalescer[%d].cpu_side_ports[%d]' % \
(shader_idx, cu_idx, tlb,
cu_idx*tlb_per_cu+tlb, 0))
else:
exec('system.cpu[%d].CUs[%d].translation_port[%d] = \
system.l1_coalescer[%d].slave[%d]' % \
system.l1_coalescer[%d].cpu_side_ports[%d]' % \
(shader_idx, cu_idx, tlb_per_cu,
cu_idx / (n_cu / num_TLBs),
cu_idx % (n_cu / num_TLBs)))
@@ -177,14 +177,14 @@ def config_tlb_hierarchy(options, system, shader_idx):
sqc_tlb_index = index / options.cu_per_sqc
sqc_tlb_port_id = index % options.cu_per_sqc
exec('system.cpu[%d].CUs[%d].sqc_tlb_port = \
system.sqc_coalescer[%d].slave[%d]' % \
system.sqc_coalescer[%d].cpu_side_ports[%d]' % \
(shader_idx, index, sqc_tlb_index, sqc_tlb_port_id))
elif name == 'scalar': # Scalar D-TLB
for index in range(n_cu):
scalar_tlb_index = index / options.cu_per_scalar_cache
scalar_tlb_port_id = index % options.cu_per_scalar_cache
exec('system.cpu[%d].CUs[%d].scalar_tlb_port = \
system.scalar_coalescer[%d].slave[%d]' % \
system.scalar_coalescer[%d].cpu_side_ports[%d]' % \
(shader_idx, index, scalar_tlb_index,
scalar_tlb_port_id))
@@ -196,11 +196,12 @@ def config_tlb_hierarchy(options, system, shader_idx):
for TLB_type in L1:
name = TLB_type['name']
for index in range(TLB_type['width']):
exec('system.%s_tlb[%d].master[0] = \
system.l2_coalescer[0].slave[%d]' % \
exec('system.%s_tlb[%d].mem_side_ports[0] = \
system.l2_coalescer[0].cpu_side_ports[%d]' % \
(name, index, l2_coalescer_index))
l2_coalescer_index += 1
# L2 <-> L3
system.l2_tlb[0].master[0] = system.l3_coalescer[0].slave[0]
system.l2_tlb[0].mem_side_ports[0] = \
system.l3_coalescer[0].cpu_side_ports[0]
return system