From 43adc5309a86b49d322781578666d21d55be76d4 Mon Sep 17 00:00:00 2001
From: Roger Chang <rogerycchang@google.com>
Date: Wed, 9 Aug 2023 16:46:57 +0800
Subject: [PATCH] arch-riscv: Add Illegal Instruction Fault Condition for RVV
 Config

Check the status.vs and misa.rvv CSR registers before executing
RVV instructions

Change-Id: I0355b94ea8ee4018be11a75aab8c19b10cb36126
---
 src/arch/riscv/isa/formats/vector_conf.isa | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/arch/riscv/isa/formats/vector_conf.isa b/src/arch/riscv/isa/formats/vector_conf.isa
index 556e230075..84e2f26783 100644
--- a/src/arch/riscv/isa/formats/vector_conf.isa
+++ b/src/arch/riscv/isa/formats/vector_conf.isa
@@ -41,6 +41,12 @@ def template VConfExecute {{
         trace::InstRecord *traceData) const
     {
         auto tc = xc->tcBase();
+        MISA misa = xc->readMiscReg(MISCREG_ISA);
+        STATUS status = xc->readMiscReg(MISCREG_STATUS);
+        if (!misa.rvv || status.vs == VPUStatus::OFF) {
+            return std::make_shared<IllegalInstFault>(
+                "RVV is disabled or VPU is off", machInst);
+        }
 
         %(op_decl)s;
         %(op_rd)s;