configs,mem-ruby: Procotol-spec. names in CHI

Use the protocol-specific controller names in CHI.

**Important**: This could change some scripts. As long as people use
CHI_config (likely), this shouldn't be a problem, but if you have a
different version of CHI_config.py locally, you will need to make the
following updates:

`Cache_Controller` -> `CHI_Cache_Controller`
`Memory_Controller` -> `CHI_Memory_Controller`

Website updates coming soon!

Change-Id: I7afdcede884ac5f9a9a76cc3d3dd35941e4e2faa
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Jason Lowe-Power
2022-03-30 17:13:24 -07:00
committed by Bobby R. Bruce
parent d56d561102
commit 42fe5accea
3 changed files with 14 additions and 14 deletions

View File

@@ -194,7 +194,7 @@ class MemCtrlMessageBuffer(MessageBuffer):
ordered = True ordered = True
class CHI_Cache_Controller(Cache_Controller): class Base_CHI_Cache_Controller(CHI_Cache_Controller):
""" """
Default parameters for a Cache controller Default parameters for a Cache controller
The Cache_Controller can also be used as a DMA requester or as The Cache_Controller can also be used as a DMA requester or as
@@ -203,7 +203,7 @@ class CHI_Cache_Controller(Cache_Controller):
def __init__(self, ruby_system): def __init__(self, ruby_system):
super().__init__( super().__init__(
version=Versions.getVersion(Cache_Controller), version=Versions.getVersion(CHI_Cache_Controller),
ruby_system=ruby_system, ruby_system=ruby_system,
mandatoryQueue=MessageBuffer(), mandatoryQueue=MessageBuffer(),
prefetchQueue=MessageBuffer(), prefetchQueue=MessageBuffer(),
@@ -223,7 +223,7 @@ class CHI_Cache_Controller(Cache_Controller):
self.sc_lock_enabled = False self.sc_lock_enabled = False
class CHI_L1Controller(CHI_Cache_Controller): class CHI_L1Controller(Base_CHI_Cache_Controller):
""" """
Default parameters for a L1 Cache controller Default parameters for a L1 Cache controller
""" """
@@ -261,7 +261,7 @@ class CHI_L1Controller(CHI_Cache_Controller):
self.unify_repl_TBEs = False self.unify_repl_TBEs = False
class CHI_L2Controller(CHI_Cache_Controller): class CHI_L2Controller(Base_CHI_Cache_Controller):
""" """
Default parameters for a L2 Cache controller Default parameters for a L2 Cache controller
""" """
@@ -298,7 +298,7 @@ class CHI_L2Controller(CHI_Cache_Controller):
self.unify_repl_TBEs = False self.unify_repl_TBEs = False
class CHI_HNFController(CHI_Cache_Controller): class CHI_HNFController(Base_CHI_Cache_Controller):
""" """
Default parameters for a coherent home node (HNF) cache controller Default parameters for a coherent home node (HNF) cache controller
""" """
@@ -336,7 +336,7 @@ class CHI_HNFController(CHI_Cache_Controller):
self.unify_repl_TBEs = False self.unify_repl_TBEs = False
class CHI_MNController(MiscNode_Controller): class CHI_MNController(Base_CHI_MiscNode_Controller):
""" """
Default parameters for a Misc Node Default parameters for a Misc Node
""" """
@@ -369,7 +369,7 @@ class CHI_MNController(MiscNode_Controller):
self.upstream_destinations = l1d_caches self.upstream_destinations = l1d_caches
class CHI_DMAController(CHI_Cache_Controller): class CHI_DMAController(Base_CHI_Cache_Controller):
""" """
Default parameters for a DMA controller Default parameters for a DMA controller
""" """
@@ -689,8 +689,8 @@ class CHI_SNF_Base(CHI_Node):
def __init__(self, ruby_system, parent): def __init__(self, ruby_system, parent):
super().__init__(ruby_system) super().__init__(ruby_system)
self._cntrl = Memory_Controller( self._cntrl = CHI_Memory_Controller(
version=Versions.getVersion(Memory_Controller), version=Versions.getVersion(CHI_Memory_Controller),
ruby_system=ruby_system, ruby_system=ruby_system,
triggerQueue=TriggerMessageBuffer(), triggerQueue=TriggerMessageBuffer(),
responseFromMemory=MemCtrlMessageBuffer(), responseFromMemory=MemCtrlMessageBuffer(),

View File

@@ -28,7 +28,7 @@ import math
from abc import abstractmethod from abc import abstractmethod
from m5.objects import ( from m5.objects import (
Cache_Controller, CHI_Cache_Controller,
MessageBuffer, MessageBuffer,
RubyNetwork, RubyNetwork,
) )
@@ -53,7 +53,7 @@ class OrderedTriggerMessageBuffer(TriggerMessageBuffer):
ordered = True ordered = True
class AbstractNode(Cache_Controller): class AbstractNode(CHI_Cache_Controller):
"""A node is the abstract unit for caches in the CHI protocol. """A node is the abstract unit for caches in the CHI protocol.
You can extend the AbstractNode to create caches (private or shared) and You can extend the AbstractNode to create caches (private or shared) and

View File

@@ -28,7 +28,7 @@ from typing import List
from m5.objects import ( from m5.objects import (
AddrRange, AddrRange,
Memory_Controller, CHI_Memory_Controller,
MessageBuffer, MessageBuffer,
Port, Port,
RubyNetwork, RubyNetwork,
@@ -48,8 +48,8 @@ class MemCtrlMessageBuffer(MessageBuffer):
ordered = True ordered = True
class MemoryController(Memory_Controller): class MemoryController(CHI_Memory_Controller):
"""A controller that connects to memory.""" """A controller that connects to memory"""
_version = 0 _version = 0