From 42b9a9666ee7b57afb8ae724d816c9a194228bd3 Mon Sep 17 00:00:00 2001 From: Vishnu Ramadas Date: Tue, 11 Jun 2024 20:35:03 -0500 Subject: [PATCH] mem-ruby: Add instSeqNum to atomic responses from GPU L2 caches This commit adds instSeqNum to the atomic responses in GPU_VIPER-TCC.sm. This will be useful when debugging issues related to GPU atomic transactions Change-Id: Ic05c8e1a1cb230abfca2759b51e5603304aadaa3 --- src/mem/ruby/protocol/GPU_VIPER-TCC.sm | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm index 9092222a4d..da4318bcf9 100644 --- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm +++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm @@ -606,6 +606,7 @@ machine(MachineType:TCC, "TCC Cache") out_msg.Destination.add(in_msg.Requestor); out_msg.Sender := machineID; out_msg.MessageSize := MessageSizeType:Response_Data; + out_msg.instSeqNum := in_msg.instSeqNum; out_msg.DataBlk := cache_entry.DataBlk; out_msg.isGLCSet := in_msg.isGLCSet; out_msg.isSLCSet := in_msg.isSLCSet;