diff --git a/src/mem/ExternalMaster.py b/src/mem/ExternalMaster.py
index 492da1dd19..44b49971a8 100644
--- a/src/mem/ExternalMaster.py
+++ b/src/mem/ExternalMaster.py
@@ -35,8 +35,10 @@
 #
 # Authors: Andrew Bardsley
 #          Curtis Dunham
+#          Christian Menard
 
 from m5.params import *
+from m5.proxy import *
 from MemObject import MemObject
 
 class ExternalMaster(MemObject):
@@ -50,3 +52,5 @@ class ExternalMaster(MemObject):
     port_data = Param.String('stub', 'A string to pass to the port'
         ' handler (in a format specific to the handler) to describe how'
         ' the port should be bound/bindable/discoverable')
+
+    system = Param.System(Parent.any, 'System this external port belongs to')
diff --git a/src/mem/external_master.cc b/src/mem/external_master.cc
index 1430199502..e0e8c1e87b 100644
--- a/src/mem/external_master.cc
+++ b/src/mem/external_master.cc
@@ -36,6 +36,7 @@
  *
  * Authors: Andrew Bardsley
  *          Curtis Dunham
+ *          Christian Menard
  */
 
 #include "mem/external_master.hh"
@@ -45,6 +46,7 @@
 
 #include "base/trace.hh"
 #include "debug/ExternalPort.hh"
+#include "sim/system.hh"
 
 std::map<std::string, ExternalMaster::Handler *>
     ExternalMaster::portHandlers;
@@ -54,7 +56,8 @@ ExternalMaster::ExternalMaster(ExternalMasterParams *params) :
     externalPort(NULL),
     portName(params->name + ".port"),
     portType(params->port_type),
-    portData(params->port_data)
+    portData(params->port_data),
+    masterId(params->system->getMasterId(params->name))
 {}
 
 BaseMasterPort &
diff --git a/src/mem/external_master.hh b/src/mem/external_master.hh
index 3a5627d49c..7303de062a 100644
--- a/src/mem/external_master.hh
+++ b/src/mem/external_master.hh
@@ -36,6 +36,7 @@
  *
  * Authors: Andrew Bardsley
  *          Curtis Dunham
+ *          Christian Menard
  */
 
 /**
@@ -129,6 +130,8 @@ class ExternalMaster : public MemObject
         Handler *handler);
 
     void init();
+
+    const MasterID masterId;
 };