X86: Get X86_FS to compile.
--HG-- extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01
This commit is contained in:
Gabe Black
@@ -37,280 +37,320 @@
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#define __DEV_NS_GIGE_REG_H__
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/* Device Register Address Map */
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#define CR 0x00
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#define CFGR 0x04
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#define MEAR 0x08
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#define PTSCR 0x0c
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#define ISR 0x10
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#define IMR 0x14
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#define IER 0x18
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#define IHR 0x1c
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#define TXDP 0x20
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#define TXDP_HI 0x24
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#define TX_CFG 0x28
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#define GPIOR 0x2c
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#define RXDP 0x30
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#define RXDP_HI 0x34
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#define RX_CFG 0x38
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#define PQCR 0x3c
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#define WCSR 0x40
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#define PCR 0x44
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#define RFCR 0x48
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#define RFDR 0x4c
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#define BRAR 0x50
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#define BRDR 0x54
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#define SRR 0x58
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#define MIBC 0x5c
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#define MIB_START 0x60
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#define MIB_END 0x88
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#define VRCR 0xbc
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#define VTCR 0xc0
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#define VDR 0xc4
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#define CCSR 0xcc
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#define TBICR 0xe0
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#define TBISR 0xe4
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#define TANAR 0xe8
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#define TANLPAR 0xec
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#define TANER 0xf0
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#define TESR 0xf4
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#define M5REG 0xf8
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#define LAST 0xf8
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#define RESERVED 0xfc
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enum DeviceRegisterAddress {
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CR = 0x00,
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CFGR = 0x04,
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MEAR = 0x08,
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PTSCR = 0x0c,
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ISR = 0x10,
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IMR = 0x14,
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IER = 0x18,
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IHR = 0x1c,
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TXDP = 0x20,
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TXDP_HI = 0x24,
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TX_CFG = 0x28,
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GPIOR = 0x2c,
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RXDP = 0x30,
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RXDP_HI = 0x34,
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RX_CFG = 0x38,
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PQCR = 0x3c,
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WCSR = 0x40,
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PCR = 0x44,
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RFCR = 0x48,
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RFDR = 0x4c,
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BRAR = 0x50,
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BRDR = 0x54,
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SRR = 0x58,
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MIBC = 0x5c,
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MIB_START = 0x60,
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MIB_END = 0x88,
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VRCR = 0xbc,
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VTCR = 0xc0,
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VDR = 0xc4,
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CCSR = 0xcc,
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TBICR = 0xe0,
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TBISR = 0xe4,
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TANAR = 0xe8,
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TANLPAR = 0xec,
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TANER = 0xf0,
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TESR = 0xf4,
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M5REG = 0xf8,
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LAST = 0xf8,
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RESERVED = 0xfc
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};
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/* Chip Command Register */
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#define CR_TXE 0x00000001
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#define CR_TXD 0x00000002
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#define CR_RXE 0x00000004
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#define CR_RXD 0x00000008
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#define CR_TXR 0x00000010
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#define CR_RXR 0x00000020
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#define CR_SWI 0x00000080
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#define CR_RST 0x00000100
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enum ChipCommandRegister {
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CR_TXE = 0x00000001,
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CR_TXD = 0x00000002,
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CR_RXE = 0x00000004,
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CR_RXD = 0x00000008,
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CR_TXR = 0x00000010,
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CR_RXR = 0x00000020,
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CR_SWI = 0x00000080,
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CR_RST = 0x00000100
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};
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/* configuration register */
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#define CFGR_LNKSTS 0x80000000
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#define CFGR_SPDSTS 0x60000000
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#define CFGR_SPDSTS1 0x40000000
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#define CFGR_SPDSTS0 0x20000000
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#define CFGR_DUPSTS 0x10000000
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#define CFGR_TBI_EN 0x01000000
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#define CFGR_RESERVED 0x0e000000
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#define CFGR_MODE_1000 0x00400000
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#define CFGR_AUTO_1000 0x00200000
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#define CFGR_PINT_CTL 0x001c0000
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#define CFGR_PINT_DUPSTS 0x00100000
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#define CFGR_PINT_LNKSTS 0x00080000
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#define CFGR_PINT_SPDSTS 0x00040000
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#define CFGR_TMRTEST 0x00020000
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#define CFGR_MRM_DIS 0x00010000
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#define CFGR_MWI_DIS 0x00008000
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#define CFGR_T64ADDR 0x00004000
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#define CFGR_PCI64_DET 0x00002000
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#define CFGR_DATA64_EN 0x00001000
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#define CFGR_M64ADDR 0x00000800
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#define CFGR_PHY_RST 0x00000400
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#define CFGR_PHY_DIS 0x00000200
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#define CFGR_EXTSTS_EN 0x00000100
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#define CFGR_REQALG 0x00000080
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#define CFGR_SB 0x00000040
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#define CFGR_POW 0x00000020
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#define CFGR_EXD 0x00000010
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#define CFGR_PESEL 0x00000008
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#define CFGR_BROM_DIS 0x00000004
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#define CFGR_EXT_125 0x00000002
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#define CFGR_BEM 0x00000001
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enum ConfigurationRegisters {
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CFGR_LNKSTS = 0x80000000,
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CFGR_SPDSTS = 0x60000000,
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CFGR_SPDSTS1 = 0x40000000,
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CFGR_SPDSTS0 = 0x20000000,
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CFGR_DUPSTS = 0x10000000,
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CFGR_TBI_EN = 0x01000000,
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CFGR_RESERVED = 0x0e000000,
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CFGR_MODE_1000 = 0x00400000,
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CFGR_AUTO_1000 = 0x00200000,
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CFGR_PINT_CTL = 0x001c0000,
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CFGR_PINT_DUPSTS = 0x00100000,
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CFGR_PINT_LNKSTS = 0x00080000,
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CFGR_PINT_SPDSTS = 0x00040000,
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CFGR_TMRTEST = 0x00020000,
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CFGR_MRM_DIS = 0x00010000,
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CFGR_MWI_DIS = 0x00008000,
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CFGR_T64ADDR = 0x00004000,
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CFGR_PCI64_DET = 0x00002000,
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CFGR_DATA64_EN = 0x00001000,
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CFGR_M64ADDR = 0x00000800,
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CFGR_PHY_RST = 0x00000400,
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CFGR_PHY_DIS = 0x00000200,
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CFGR_EXTSTS_EN = 0x00000100,
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CFGR_REQALG = 0x00000080,
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CFGR_SB = 0x00000040,
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CFGR_POW = 0x00000020,
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CFGR_EXD = 0x00000010,
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CFGR_PESEL = 0x00000008,
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CFGR_BROM_DIS = 0x00000004,
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CFGR_EXT_125 = 0x00000002,
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CFGR_BEM = 0x00000001
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};
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/* EEPROM access register */
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#define MEAR_EEDI 0x00000001
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#define MEAR_EEDO 0x00000002
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#define MEAR_EECLK 0x00000004
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#define MEAR_EESEL 0x00000008
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#define MEAR_MDIO 0x00000010
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#define MEAR_MDDIR 0x00000020
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#define MEAR_MDC 0x00000040
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enum EEPROMAccessRegister {
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MEAR_EEDI = 0x00000001,
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MEAR_EEDO = 0x00000002,
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MEAR_EECLK = 0x00000004,
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MEAR_EESEL = 0x00000008,
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MEAR_MDIO = 0x00000010,
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MEAR_MDDIR = 0x00000020,
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MEAR_MDC = 0x00000040,
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};
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/* PCI test control register */
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#define PTSCR_EEBIST_FAIL 0x00000001
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#define PTSCR_EEBIST_EN 0x00000002
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#define PTSCR_EELOAD_EN 0x00000004
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#define PTSCR_RBIST_FAIL 0x000001b8
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#define PTSCR_RBIST_DONE 0x00000200
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#define PTSCR_RBIST_EN 0x00000400
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#define PTSCR_RBIST_RST 0x00002000
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#define PTSCR_RBIST_RDONLY 0x000003f9
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enum PCITestControlRegister {
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PTSCR_EEBIST_FAIL = 0x00000001,
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PTSCR_EEBIST_EN = 0x00000002,
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PTSCR_EELOAD_EN = 0x00000004,
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PTSCR_RBIST_FAIL = 0x000001b8,
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PTSCR_RBIST_DONE = 0x00000200,
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PTSCR_RBIST_EN = 0x00000400,
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PTSCR_RBIST_RST = 0x00002000,
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PTSCR_RBIST_RDONLY = 0x000003f9
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};
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/* interrupt status register */
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#define ISR_RESERVE 0x80000000
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#define ISR_TXDESC3 0x40000000
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#define ISR_TXDESC2 0x20000000
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#define ISR_TXDESC1 0x10000000
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#define ISR_TXDESC0 0x08000000
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#define ISR_RXDESC3 0x04000000
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#define ISR_RXDESC2 0x02000000
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#define ISR_RXDESC1 0x01000000
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#define ISR_RXDESC0 0x00800000
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#define ISR_TXRCMP 0x00400000
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#define ISR_RXRCMP 0x00200000
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#define ISR_DPERR 0x00100000
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#define ISR_SSERR 0x00080000
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#define ISR_RMABT 0x00040000
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#define ISR_RTABT 0x00020000
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#define ISR_RXSOVR 0x00010000
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#define ISR_HIBINT 0x00008000
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#define ISR_PHY 0x00004000
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#define ISR_PME 0x00002000
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#define ISR_SWI 0x00001000
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#define ISR_MIB 0x00000800
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#define ISR_TXURN 0x00000400
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#define ISR_TXIDLE 0x00000200
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#define ISR_TXERR 0x00000100
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#define ISR_TXDESC 0x00000080
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#define ISR_TXOK 0x00000040
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#define ISR_RXORN 0x00000020
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#define ISR_RXIDLE 0x00000010
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#define ISR_RXEARLY 0x00000008
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#define ISR_RXERR 0x00000004
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#define ISR_RXDESC 0x00000002
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#define ISR_RXOK 0x00000001
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#define ISR_ALL 0x7FFFFFFF
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#define ISR_DELAY (ISR_TXIDLE|ISR_TXDESC|ISR_TXOK| \
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ISR_RXIDLE|ISR_RXDESC|ISR_RXOK)
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#define ISR_NODELAY (ISR_ALL & ~ISR_DELAY)
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#define ISR_IMPL (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \
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ISR_RXIDLE|ISR_RXDESC|ISR_RXOK)
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#define ISR_NOIMPL (ISR_ALL & ~ISR_IMPL)
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enum InterruptStatusRegister {
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ISR_RESERVE = 0x80000000,
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ISR_TXDESC3 = 0x40000000,
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ISR_TXDESC2 = 0x20000000,
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ISR_TXDESC1 = 0x10000000,
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ISR_TXDESC0 = 0x08000000,
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ISR_RXDESC3 = 0x04000000,
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ISR_RXDESC2 = 0x02000000,
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ISR_RXDESC1 = 0x01000000,
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ISR_RXDESC0 = 0x00800000,
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ISR_TXRCMP = 0x00400000,
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ISR_RXRCMP = 0x00200000,
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ISR_DPERR = 0x00100000,
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ISR_SSERR = 0x00080000,
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ISR_RMABT = 0x00040000,
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ISR_RTAB = 0x00020000,
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ISR_RXSOVR = 0x00010000,
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ISR_HIBINT = 0x00008000,
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ISR_PHY = 0x00004000,
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ISR_PME = 0x00002000,
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ISR_SWI = 0x00001000,
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ISR_MIB = 0x00000800,
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ISR_TXURN = 0x00000400,
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ISR_TXIDLE = 0x00000200,
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ISR_TXERR = 0x00000100,
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ISR_TXDESC = 0x00000080,
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ISR_TXOK = 0x00000040,
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ISR_RXORN = 0x00000020,
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ISR_RXIDLE = 0x00000010,
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ISR_RXEARLY = 0x00000008,
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ISR_RXERR = 0x00000004,
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ISR_RXDESC = 0x00000002,
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ISR_RXOK = 0x00000001,
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ISR_ALL = 0x7FFFFFFF,
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ISR_DELAY = (ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|
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ISR_RXIDLE|ISR_RXDESC|ISR_RXOK),
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ISR_NODELAY = (ISR_ALL & ~ISR_DELAY),
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ISR_IMPL = (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN|
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ISR_RXIDLE|ISR_RXDESC|ISR_RXOK),
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ISR_NOIMPL = (ISR_ALL & ~ISR_IMPL)
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};
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/* transmit configuration register */
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#define TX_CFG_CSI 0x80000000
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#define TX_CFG_HBI 0x40000000
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#define TX_CFG_MLB 0x20000000
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#define TX_CFG_ATP 0x10000000
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#define TX_CFG_ECRETRY 0x00800000
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#define TX_CFG_BRST_DIS 0x00080000
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#define TX_CFG_MXDMA1024 0x00000000
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#define TX_CFG_MXDMA512 0x00700000
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#define TX_CFG_MXDMA256 0x00600000
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#define TX_CFG_MXDMA128 0x00500000
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#define TX_CFG_MXDMA64 0x00400000
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#define TX_CFG_MXDMA32 0x00300000
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#define TX_CFG_MXDMA16 0x00200000
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#define TX_CFG_MXDMA8 0x00100000
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#define TX_CFG_MXDMA 0x00700000
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enum TransmitConfigurationRegister {
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TX_CFG_CSI = 0x80000000,
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TX_CFG_HBI = 0x40000000,
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TX_CFG_MLB = 0x20000000,
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TX_CFG_ATP = 0x10000000,
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TX_CFG_ECRETRY = 0x00800000,
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TX_CFG_BRST_DIS = 0x00080000,
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TX_CFG_MXDMA1024 = 0x00000000,
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TX_CFG_MXDMA512 = 0x00700000,
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TX_CFG_MXDMA256 = 0x00600000,
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TX_CFG_MXDMA128 = 0x00500000,
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TX_CFG_MXDMA64 = 0x00400000,
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TX_CFG_MXDMA32 = 0x00300000,
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TX_CFG_MXDMA16 = 0x00200000,
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TX_CFG_MXDMA8 = 0x00100000,
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TX_CFG_MXDMA = 0x00700000,
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#define TX_CFG_FLTH_MASK 0x0000ff00
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#define TX_CFG_DRTH_MASK 0x000000ff
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TX_CFG_FLTH_MASK = 0x0000ff00,
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TX_CFG_DRTH_MASK = 0x000000ff
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};
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/*general purpose I/O control register */
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#define GPIOR_UNUSED 0xffff8000
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#define GPIOR_GP5_IN 0x00004000
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#define GPIOR_GP4_IN 0x00002000
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#define GPIOR_GP3_IN 0x00001000
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#define GPIOR_GP2_IN 0x00000800
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#define GPIOR_GP1_IN 0x00000400
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#define GPIOR_GP5_OE 0x00000200
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#define GPIOR_GP4_OE 0x00000100
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#define GPIOR_GP3_OE 0x00000080
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#define GPIOR_GP2_OE 0x00000040
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#define GPIOR_GP1_OE 0x00000020
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#define GPIOR_GP5_OUT 0x00000010
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#define GPIOR_GP4_OUT 0x00000008
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#define GPIOR_GP3_OUT 0x00000004
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#define GPIOR_GP2_OUT 0x00000002
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#define GPIOR_GP1_OUT 0x00000001
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enum GeneralPurposeIOControlRegister {
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GPIOR_UNUSED = 0xffff8000,
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GPIOR_GP5_IN = 0x00004000,
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GPIOR_GP4_IN = 0x00002000,
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GPIOR_GP3_IN = 0x00001000,
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GPIOR_GP2_IN = 0x00000800,
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GPIOR_GP1_IN = 0x00000400,
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GPIOR_GP5_OE = 0x00000200,
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GPIOR_GP4_OE = 0x00000100,
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GPIOR_GP3_OE = 0x00000080,
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GPIOR_GP2_OE = 0x00000040,
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GPIOR_GP1_OE = 0x00000020,
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GPIOR_GP5_OUT = 0x00000010,
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GPIOR_GP4_OUT = 0x00000008,
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GPIOR_GP3_OUT = 0x00000004,
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GPIOR_GP2_OUT = 0x00000002,
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GPIOR_GP1_OUT = 0x00000001
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};
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/* receive configuration register */
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#define RX_CFG_AEP 0x80000000
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#define RX_CFG_ARP 0x40000000
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#define RX_CFG_STRIPCRC 0x20000000
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#define RX_CFG_RX_FD 0x10000000
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#define RX_CFG_ALP 0x08000000
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#define RX_CFG_AIRL 0x04000000
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#define RX_CFG_MXDMA512 0x00700000
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#define RX_CFG_MXDMA 0x00700000
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#define RX_CFG_DRTH 0x0000003e
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#define RX_CFG_DRTH0 0x00000002
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enum ReceiveConfigurationRegister {
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RX_CFG_AEP = 0x80000000,
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RX_CFG_ARP = 0x40000000,
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RX_CFG_STRIPCRC = 0x20000000,
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RX_CFG_RX_FD = 0x10000000,
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RX_CFG_ALP = 0x08000000,
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RX_CFG_AIRL = 0x04000000,
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RX_CFG_MXDMA512 = 0x00700000,
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RX_CFG_MXDMA = 0x00700000,
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RX_CFG_DRTH = 0x0000003e,
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RX_CFG_DRTH0 = 0x00000002
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};
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/* pause control status register */
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#define PCR_PSEN (1 << 31)
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#define PCR_PS_MCAST (1 << 30)
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#define PCR_PS_DA (1 << 29)
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#define PCR_STHI_8 (3 << 23)
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#define PCR_STLO_4 (1 << 23)
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#define PCR_FFHI_8K (3 << 21)
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#define PCR_FFLO_4K (1 << 21)
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#define PCR_PAUSE_CNT 0xFFFE
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enum PauseControlStatusRegister {
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PCR_PSEN = (1 << 31),
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PCR_PS_MCAST = (1 << 30),
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PCR_PS_DA = (1 << 29),
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PCR_STHI_8 = (3 << 23),
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PCR_STLO_4 = (1 << 23),
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PCR_FFHI_8K = (3 << 21),
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PCR_FFLO_4K = (1 << 21),
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PCR_PAUSE_CNT = 0xFFFE
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};
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|
||||
/*receive filter/match control register */
|
||||
#define RFCR_RFEN 0x80000000
|
||||
#define RFCR_AAB 0x40000000
|
||||
#define RFCR_AAM 0x20000000
|
||||
#define RFCR_AAU 0x10000000
|
||||
#define RFCR_APM 0x08000000
|
||||
#define RFCR_APAT 0x07800000
|
||||
#define RFCR_APAT3 0x04000000
|
||||
#define RFCR_APAT2 0x02000000
|
||||
#define RFCR_APAT1 0x01000000
|
||||
#define RFCR_APAT0 0x00800000
|
||||
#define RFCR_AARP 0x00400000
|
||||
#define RFCR_MHEN 0x00200000
|
||||
#define RFCR_UHEN 0x00100000
|
||||
#define RFCR_ULM 0x00080000
|
||||
#define RFCR_RFADDR 0x000003ff
|
||||
enum ReceiveFilterMatchControlRegister {
|
||||
RFCR_RFEN = 0x80000000,
|
||||
RFCR_AAB = 0x40000000,
|
||||
RFCR_AAM = 0x20000000,
|
||||
RFCR_AAU = 0x10000000,
|
||||
RFCR_APM = 0x08000000,
|
||||
RFCR_APAT = 0x07800000,
|
||||
RFCR_APAT3 = 0x04000000,
|
||||
RFCR_APAT2 = 0x02000000,
|
||||
RFCR_APAT1 = 0x01000000,
|
||||
RFCR_APAT0 = 0x00800000,
|
||||
RFCR_AARP = 0x00400000,
|
||||
RFCR_MHEN = 0x00200000,
|
||||
RFCR_UHEN = 0x00100000,
|
||||
RFCR_ULM = 0x00080000,
|
||||
RFCR_RFADDR = 0x000003ff
|
||||
};
|
||||
|
||||
/* receive filter/match data register */
|
||||
#define RFDR_BMASK 0x00030000
|
||||
#define RFDR_RFDATA0 0x000000ff
|
||||
#define RFDR_RFDATA1 0x0000ff00
|
||||
enum ReceiveFilterMatchDataRegister {
|
||||
RFDR_BMASK = 0x00030000,
|
||||
RFDR_RFDATA0 = 0x000000ff,
|
||||
RFDR_RFDATA1 = 0x0000ff00
|
||||
};
|
||||
|
||||
/* management information base control register */
|
||||
#define MIBC_MIBS 0x00000008
|
||||
#define MIBC_ACLR 0x00000004
|
||||
#define MIBC_FRZ 0x00000002
|
||||
#define MIBC_WRN 0x00000001
|
||||
enum ManagementInformationBaseControlRegister {
|
||||
MIBC_MIBS = 0x00000008,
|
||||
MIBC_ACLR = 0x00000004,
|
||||
MIBC_FRZ = 0x00000002,
|
||||
MIBC_WRN = 0x00000001
|
||||
};
|
||||
|
||||
/* VLAN/IP receive control register */
|
||||
#define VRCR_RUDPE 0x00000080
|
||||
#define VRCR_RTCPE 0x00000040
|
||||
#define VRCR_RIPE 0x00000020
|
||||
#define VRCR_IPEN 0x00000010
|
||||
#define VRCR_DUTF 0x00000008
|
||||
#define VRCR_DVTF 0x00000004
|
||||
#define VRCR_VTREN 0x00000002
|
||||
#define VRCR_VTDEN 0x00000001
|
||||
enum VLANIPReceiveControlRegister {
|
||||
VRCR_RUDPE = 0x00000080,
|
||||
VRCR_RTCPE = 0x00000040,
|
||||
VRCR_RIPE = 0x00000020,
|
||||
VRCR_IPEN = 0x00000010,
|
||||
VRCR_DUTF = 0x00000008,
|
||||
VRCR_DVTF = 0x00000004,
|
||||
VRCR_VTREN = 0x00000002,
|
||||
VRCR_VTDEN = 0x00000001
|
||||
};
|
||||
|
||||
/* VLAN/IP transmit control register */
|
||||
#define VTCR_PPCHK 0x00000008
|
||||
#define VTCR_GCHK 0x00000004
|
||||
#define VTCR_VPPTI 0x00000002
|
||||
#define VTCR_VGTI 0x00000001
|
||||
enum VLANIPTransmitControlRegister {
|
||||
VTCR_PPCHK = 0x00000008,
|
||||
VTCR_GCHK = 0x00000004,
|
||||
VTCR_VPPTI = 0x00000002,
|
||||
VTCR_VGTI = 0x00000001
|
||||
};
|
||||
|
||||
/* Clockrun Control/Status Register */
|
||||
#define CCSR_CLKRUN_EN 0x00000001
|
||||
enum ClockrunControlStatusRegister {
|
||||
CCSR_CLKRUN_EN = 0x00000001
|
||||
};
|
||||
|
||||
/* TBI control register */
|
||||
#define TBICR_MR_LOOPBACK 0x00004000
|
||||
#define TBICR_MR_AN_ENABLE 0x00001000
|
||||
#define TBICR_MR_RESTART_AN 0x00000200
|
||||
enum TBIControlRegister {
|
||||
TBICR_MR_LOOPBACK = 0x00004000,
|
||||
TBICR_MR_AN_ENABLE = 0x00001000,
|
||||
TBICR_MR_RESTART_AN = 0x00000200
|
||||
};
|
||||
|
||||
/* TBI status register */
|
||||
#define TBISR_MR_LINK_STATUS 0x00000020
|
||||
#define TBISR_MR_AN_COMPLETE 0x00000004
|
||||
enum TBIStatusRegister {
|
||||
TBISR_MR_LINK_STATUS = 0x00000020,
|
||||
TBISR_MR_AN_COMPLETE = 0x00000004
|
||||
};
|
||||
|
||||
/* TBI auto-negotiation advertisement register */
|
||||
#define TANAR_NP 0x00008000
|
||||
#define TANAR_RF2 0x00002000
|
||||
#define TANAR_RF1 0x00001000
|
||||
#define TANAR_PS2 0x00000100
|
||||
#define TANAR_PS1 0x00000080
|
||||
#define TANAR_HALF_DUP 0x00000040
|
||||
#define TANAR_FULL_DUP 0x00000020
|
||||
#define TANAR_UNUSED 0x00000E1F
|
||||
enum TBIAutoNegotiationAdvertisementRegister {
|
||||
TANAR_NP = 0x00008000,
|
||||
TANAR_RF2 = 0x00002000,
|
||||
TANAR_RF1 = 0x00001000,
|
||||
TANAR_PS2 = 0x00000100,
|
||||
TANAR_PS1 = 0x00000080,
|
||||
TANAR_HALF_DUP = 0x00000040,
|
||||
TANAR_FULL_DUP = 0x00000020,
|
||||
TANAR_UNUSED = 0x00000E1F
|
||||
};
|
||||
|
||||
/* M5 control register */
|
||||
#define M5REG_RESERVED 0xfffffffc
|
||||
#define M5REG_RSS 0x00000004
|
||||
#define M5REG_RX_THREAD 0x00000002
|
||||
#define M5REG_TX_THREAD 0x00000001
|
||||
enum M5ControlRegister {
|
||||
M5REG_RESERVED = 0xfffffffc,
|
||||
M5REG_RSS = 0x00000004,
|
||||
M5REG_RX_THREAD = 0x00000002,
|
||||
M5REG_TX_THREAD = 0x00000001
|
||||
};
|
||||
|
||||
struct ns_desc32 {
|
||||
uint32_t link; /* link field to next descriptor in linked list */
|
||||
@@ -327,27 +367,35 @@ struct ns_desc64 {
|
||||
};
|
||||
|
||||
/* cmdsts flags for descriptors */
|
||||
#define CMDSTS_OWN 0x80000000
|
||||
#define CMDSTS_MORE 0x40000000
|
||||
#define CMDSTS_INTR 0x20000000
|
||||
#define CMDSTS_ERR 0x10000000
|
||||
#define CMDSTS_OK 0x08000000
|
||||
#define CMDSTS_LEN_MASK 0x0000ffff
|
||||
enum CMDSTSFlatsForDescriptors {
|
||||
CMDSTS_OWN = 0x80000000,
|
||||
CMDSTS_MORE = 0x40000000,
|
||||
CMDSTS_INTR = 0x20000000,
|
||||
CMDSTS_ERR = 0x10000000,
|
||||
CMDSTS_OK = 0x08000000,
|
||||
CMDSTS_LEN_MASK = 0x0000ffff,
|
||||
|
||||
#define CMDSTS_DEST_MASK 0x01800000
|
||||
#define CMDSTS_DEST_SELF 0x00800000
|
||||
#define CMDSTS_DEST_MULTI 0x01000000
|
||||
CMDSTS_DEST_MASK = 0x01800000,
|
||||
CMDSTS_DEST_SELF = 0x00800000,
|
||||
CMDSTS_DEST_MULTI = 0x01000000
|
||||
};
|
||||
|
||||
/* extended flags for descriptors */
|
||||
#define EXTSTS_UDPERR 0x00400000
|
||||
#define EXTSTS_UDPPKT 0x00200000
|
||||
#define EXTSTS_TCPERR 0x00100000
|
||||
#define EXTSTS_TCPPKT 0x00080000
|
||||
#define EXTSTS_IPERR 0x00040000
|
||||
#define EXTSTS_IPPKT 0x00020000
|
||||
|
||||
enum ExtendedFlagsForDescriptors {
|
||||
EXTSTS_UDPERR = 0x00400000,
|
||||
EXTSTS_UDPPKT = 0x00200000,
|
||||
EXTSTS_TCPERR = 0x00100000,
|
||||
EXTSTS_TCPPKT = 0x00080000,
|
||||
EXTSTS_IPERR = 0x00040000,
|
||||
EXTSTS_IPPKT = 0x00020000
|
||||
};
|
||||
|
||||
/* speed status */
|
||||
#define SPDSTS_POLARITY (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS | (lnksts ? CFGR_LNKSTS : 0))
|
||||
static inline int
|
||||
SPDSTS_POLARITY(int lnksts)
|
||||
{
|
||||
return (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS |
|
||||
(lnksts ? CFGR_LNKSTS : 0));
|
||||
}
|
||||
|
||||
#endif /* __DEV_NS_GIGE_REG_H__ */
|
||||
|
||||
Reference in New Issue
Block a user