From 404bf901d074b186ea70831f476d50374a78c0dd Mon Sep 17 00:00:00 2001 From: Mahyar Samani Date: Wed, 24 Nov 2021 16:23:22 -0800 Subject: [PATCH] tests: Adding MultiChannelMemory to riscv-boot This change adds MultiChannelMemory to the tests for full system risc-v. Change-Id: I3e9b6f7ac539c24ca9694c1c49afa09d0cecca2f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53303 Maintainer: Bobby Bruce Reviewed-by: Bobby Bruce Tested-by: kokoro --- tests/gem5/configs/riscv_boot_exit_run.py | 22 ++++-- .../gem5/riscv-boot-tests/test_linux_boot.py | 78 +++++++++++-------- 2 files changed, 63 insertions(+), 37 deletions(-) diff --git a/tests/gem5/configs/riscv_boot_exit_run.py b/tests/gem5/configs/riscv_boot_exit_run.py index 8add619386..45ce62c44a 100644 --- a/tests/gem5/configs/riscv_boot_exit_run.py +++ b/tests/gem5/configs/riscv_boot_exit_run.py @@ -36,15 +36,15 @@ Characteristics import m5 from m5.objects import Root -from gem5.components.boards.riscv_board import RiscvBoard -from gem5.components.memory.single_channel import SingleChannelDDR3_1600 -from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.utils.requires import requires from gem5.resources.resource import Resource +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.boards.riscv_board import RiscvBoard +from gem5.components.processors.simple_processor import SimpleProcessor import argparse +import importlib parser = argparse.ArgumentParser( description="A script to run the RISCV boot exit tests." @@ -76,6 +76,14 @@ parser.add_argument( help="The memory system.", ) +parser.add_argument( + "-d", + "--dram-class", + type=str, + required=True, + help="The python class for the memory interface to use" +) + parser.add_argument( "-t", "--tick-exit", @@ -117,7 +125,11 @@ elif args.mem_system == "mi_example": ) # Setup the system memory. -memory = SingleChannelDDR3_1600() +python_module = "gem5.components.memory.multi_channel" +memory_class = getattr( + importlib.import_module(python_module), args.dram_class +) +memory = memory_class(size="4GiB") # Setup a processor. if args.cpu == "kvm": diff --git a/tests/gem5/riscv-boot-tests/test_linux_boot.py b/tests/gem5/riscv-boot-tests/test_linux_boot.py index 9eb9ae3bf9..6d4e9f16fe 100644 --- a/tests/gem5/riscv-boot-tests/test_linux_boot.py +++ b/tests/gem5/riscv-boot-tests/test_linux_boot.py @@ -40,12 +40,13 @@ def test_boot( cpu: str, num_cpus: int, cache_type: str, + memory_class: str, length: str, to_tick: Optional[int] = None, ): - name = "{}-cpu_{}-{}-cores_riscv-boot-test".format( - cpu, str(num_cpus), cache_type) + name = "{}-cpu_{}-cores_{}_{}_riscv-boot-test".format( + cpu, str(num_cpus), cache_type, memory_class) verifiers = [] exit_regex = re.compile( @@ -62,6 +63,8 @@ def test_boot( str(num_cpus), "--mem-system", cache_type, + "--dram-class", + memory_class, "--resource-directory", resource_path, ] @@ -94,6 +97,7 @@ test_boot( cpu="atomic", num_cpus=1, cache_type="classic", + memory_class="SingleChannelDDR3_1600", length=constants.quick_tag, to_tick=10000000000, # Simulates 1/100th of a second. ) @@ -102,6 +106,7 @@ test_boot( cpu="timing", num_cpus=1, cache_type="classic", + memory_class="SingleChannelDDR3_2133", length=constants.quick_tag, to_tick=10000000000, ) @@ -110,6 +115,7 @@ test_boot( cpu="timing", num_cpus=1, cache_type="mi_example", + memory_class="SingleChannelDDR4_2400", length=constants.quick_tag, to_tick=10000000000, ) @@ -118,6 +124,7 @@ test_boot( cpu="o3", num_cpus=1, cache_type="classic", + memory_class="DualChannelDDR3_1600", length=constants.quick_tag, to_tick=10000000000, ) @@ -126,6 +133,7 @@ test_boot( cpu="timing", num_cpus=4, cache_type="classic", + memory_class="DualChannelDDR3_2133", length=constants.quick_tag, to_tick=10000000000, ) @@ -134,6 +142,7 @@ test_boot( cpu="timing", num_cpus=4, cache_type="mi_example", + memory_class="DualChannelDDR4_2400", length=constants.quick_tag, to_tick=10000000000, ) @@ -144,37 +153,42 @@ test_boot( # https://gem5.atlassian.net/browse/GEM5-1120, these tests have been disabled # until the exact error causing the Nightly tests to timeout is established. -#test_boot( -# cpu="atomic", -# num_cpus=1, -# cache_type="classic", -# length=constants.long_tag, -#) +# test_boot( +# cpu="atomic", +# num_cpus=1, +# cache_type="classic", +# memory_class="HBM2Stack", +# length=constants.long_tag, +# ) -#test_boot( -# cpu="timing", -# num_cpus=1, -# cache_type="mi_example", -# length=constants.long_tag, -#) +# test_boot( +# cpu="timing", +# num_cpus=1, +# cache_type="mi_example", +# memory_class="SingleChannelLPDDR3_1600", +# length=constants.long_tag, +# ) -#test_boot( -# cpu="timing", -# num_cpus=4, -# cache_type="mi_example", -# length=constants.long_tag, -#) +# test_boot( +# cpu="timing", +# num_cpus=4, +# cache_type="mi_example", +# memory_class="DualChannelDDR4_2400", +# length=constants.long_tag, +# ) -#test_boot( -# cpu="atomic", -# num_cpus=4, -# cache_type="classic", -# length=constants.long_tag, -#) +# test_boot( +# cpu="atomic", +# num_cpus=4, +# cache_type="classic", +# memory_class="DualChannelLPDDR3_1600", +# length=constants.long_tag, +# ) -#test_boot( -# cpu="o3", -# num_cpus=8, -# cache_type="mi_example", -# length=constants.long_tag, -#) +# test_boot( +# cpu="o3", +# num_cpus=8, +# cache_type="mi_example", +# memory_class="HBM2Stack", +# length=constants.long_tag, +# )