From 3fec0f9ca3e3c4b2514ece623d7fad3f6f50c683 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 29 Apr 2022 16:36:17 +0100 Subject: [PATCH] system-arm: Detect the GICv3 redistributor stride at runtime Some platforms are not GICv4 compatible, therefore we need to make sure the stride between redistributors is configurable: 2 frames of 64KiB for GICv3 => a stride of 128KiB 4 frames of 64KiB for GICv4 => a stride of 256KiB We detect this at runtime by reading the GICD_PIDR2.ArchRev bitfield This is 3 for GICv3 and 4 for GICv4. Note: other software projects [1] rely on a different check, mainly reading the GICR_TYPER.VLPIS bit We diverge from this behaviour as VLPIS are not implemented and we do not want to incorrectly report this to the probing software. We should move to VLPIS once they get implemented [1]: https://github.com/torvalds/linux/blob/\ 107c948d1d3e61d10aee9d0f7c3d81bbee9842af/\ drivers/irqchip/irq-gic-v3.c#L864 Change-Id: I7cc554f48cc6a347c03ed80cf2ea320f618a59c2 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59394 Tested-by: kokoro Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- system/arm/bootloader/arm64/boot.S | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/system/arm/bootloader/arm64/boot.S b/system/arm/bootloader/arm64/boot.S index f1c286428b..2499afee2f 100644 --- a/system/arm/bootloader/arm64/boot.S +++ b/system/arm/bootloader/arm64/boot.S @@ -80,10 +80,15 @@ _start: ldr x1, =GIC_DIST_BASE // GICD_CTLR mov w0, #7 // EnableGrp0 | EnableGrp1NS | EnableGrp1S str w0, [x1] - + mov x2, #0xffe8 + ldr w2, [x1, x2] // GICD_PIDR2 + and w3, w2, #0xf0 // GICD_PIDR2.Read ArchRev + cmp w3, #0x30 // Check if GICv3 + mov w4, #0x20000 // 128KiB redistributor stride + mov w5, #0x40000 // 256KiB redistributor stride + csel w2, w4, w5, eq // Select the correct redistributor stride ldr x1, =GIC_REDIST_BASE - mov x2, #1 << 18 // GICv4 mov w0, #~0 // Grp1 interrupts 1: add x5, x1, #0x10000 // SGI base str w0, [x5, #0x80] // GICR_IGROUPR0