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MEM: Separate requests and responses for timing accesses

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This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.

For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).

The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.

With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
This commit is contained in:
Andreas Hansson
2012-05-01 13:40:42 -04:00
parent 8966e6d36d
commit 3fea59e162
47 changed files with 546 additions and 424 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/base.cc
View File

@@ -532,7 +532,7 @@ BaseCPU::traceFunctionsInternal(Addr pc)
}
bool
BaseCPU::CpuPort::recvTiming(PacketPtr pkt)
BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt)
{
panic("BaseCPU doesn't expect recvTiming!\n");
return true;

2
src/cpu/base.hh
View File

@@ -133,7 +133,7 @@ class BaseCPU : public MemObject
protected:
virtual bool recvTiming(PacketPtr pkt);
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvRetry();

4
src/cpu/inorder/cpu.cc
View File

@@ -88,10 +88,8 @@ InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit) :
{ }
bool
InOrderCPU::CachePort::recvTiming(Packet *pkt)
InOrderCPU::CachePort::recvTimingResp(Packet *pkt)
{
assert(pkt->isResponse());
if (pkt->isError())
DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
pkt->getAddr());

4
src/cpu/inorder/cpu.hh
View File

@@ -170,13 +170,13 @@ class InOrderCPU : public BaseCPU
protected:
/** Timing version of receive */
bool recvTiming(PacketPtr pkt);
bool recvTimingResp(PacketPtr pkt);
/** Handles doing a retry of a failed timing request. */
void recvRetry();
/** Ignoring snoops for now. */
bool recvTimingSnoop(PacketPtr pkt) { return true; }
void recvTimingSnoopReq(PacketPtr pkt) { }
};
/** Define TickEvent for the CPU */

2
src/cpu/inorder/resources/cache_unit.cc
View File

@@ -873,7 +873,7 @@ CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res,
tid, inst->seqNum, cache_req->dataPkt->getAddr());
if (do_access) {
if (!cachePort->sendTiming(cache_req->dataPkt)) {
if (!cachePort->sendTimingReq(cache_req->dataPkt)) {
DPRINTF(InOrderCachePort,
"[tid:%i] [sn:%i] cannot access cache, because port "
"is blocked. now waiting to retry request\n", tid,

15
src/cpu/o3/cpu.cc
View File

@@ -87,9 +87,8 @@ BaseO3CPU::regStats()
template<class Impl>
bool
FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
{
assert(pkt->isResponse());
DPRINTF(O3CPU, "Fetch unit received timing\n");
// We shouldn't ever get a block in ownership state
assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
@@ -107,18 +106,16 @@ FullO3CPU<Impl>::IcachePort::recvRetry()
template <class Impl>
bool
FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
{
assert(pkt->isResponse());
return lsq->recvTiming(pkt);
return lsq->recvTimingResp(pkt);
}
template <class Impl>
bool
FullO3CPU<Impl>::DcachePort::recvTimingSnoop(PacketPtr pkt)
void
FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
{
assert(pkt->isRequest());
return lsq->recvTimingSnoop(pkt);
lsq->recvTimingSnoopReq(pkt);
}
template <class Impl>

8
src/cpu/o3/cpu.hh
View File

@@ -148,8 +148,8 @@ class FullO3CPU : public BaseO3CPU
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
virtual bool recvTiming(PacketPtr pkt);
virtual bool recvTimingSnoop(PacketPtr pkt) { return true; }
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvTimingSnoopReq(PacketPtr pkt) { }
/** Handles doing a retry of a failed fetch. */
virtual void recvRetry();
@@ -176,8 +176,8 @@ class FullO3CPU : public BaseO3CPU
/** Timing version of receive. Handles writing back and
* completing the load or store that has returned from
* memory. */
virtual bool recvTiming(PacketPtr pkt);
virtual bool recvTimingSnoop(PacketPtr pkt);
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvTimingSnoopReq(PacketPtr pkt);
/** Handles doing a retry of the previous send. */
virtual void recvRetry();

4
src/cpu/o3/fetch_impl.hh
View File

@@ -621,7 +621,7 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
fetchedCacheLines++;
// Access the cache.
if (!cpu->getInstPort().sendTiming(data_pkt)) {
if (!cpu->getInstPort().sendTimingReq(data_pkt)) {
assert(retryPkt == NULL);
assert(retryTid == InvalidThreadID);
DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
@@ -1356,7 +1356,7 @@ DefaultFetch<Impl>::recvRetry()
assert(retryTid != InvalidThreadID);
assert(fetchStatus[retryTid] == IcacheWaitRetry);
if (cpu->getInstPort().sendTiming(retryPkt)) {
if (cpu->getInstPort().sendTimingReq(retryPkt)) {
fetchStatus[retryTid] = IcacheWaitResponse;
retryPkt = NULL;
retryTid = InvalidThreadID;

4
src/cpu/o3/lsq.hh
View File

@@ -297,9 +297,9 @@ class LSQ {
*
* @param pkt Response packet from the memory sub-system
*/
bool recvTiming(PacketPtr pkt);
bool recvTimingResp(PacketPtr pkt);
bool recvTimingSnoop(PacketPtr pkt);
void recvTimingSnoopReq(PacketPtr pkt);
/** The CPU pointer. */
O3CPU *cpu;

11
src/cpu/o3/lsq_impl.hh
View File

@@ -319,9 +319,8 @@ LSQ<Impl>::recvRetry()
template <class Impl>
bool
LSQ<Impl>::recvTiming(PacketPtr pkt)
LSQ<Impl>::recvTimingResp(PacketPtr pkt)
{
assert(pkt->isResponse());
if (pkt->isError())
DPRINTF(LSQ, "Got error packet back for address: %#X\n",
pkt->getAddr());
@@ -330,10 +329,9 @@ LSQ<Impl>::recvTiming(PacketPtr pkt)
}
template <class Impl>
bool
LSQ<Impl>::recvTimingSnoop(PacketPtr pkt)
void
LSQ<Impl>::recvTimingSnoopReq(PacketPtr pkt)
{
assert(pkt->isRequest());
DPRINTF(LSQ, "received pkt for addr:%#x %s\n", pkt->getAddr(),
pkt->cmdString());
@@ -345,9 +343,6 @@ LSQ<Impl>::recvTimingSnoop(PacketPtr pkt)
thread[tid].checkSnoop(pkt);
}
}
// to provide stronger consistency model
return true;
}
template<class Impl>

4
src/cpu/o3/lsq_unit.hh
View File

@@ -801,7 +801,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
state->mainPkt = data_pkt;
}
if (!dcachePort->sendTiming(fst_data_pkt)) {
if (!dcachePort->sendTimingReq(fst_data_pkt)) {
// Delete state and data packet because a load retry
// initiates a pipeline restart; it does not retry.
delete state;
@@ -830,7 +830,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
// The first packet will return in completeDataAccess and be
// handled there.
++usedPorts;
if (!dcachePort->sendTiming(snd_data_pkt)) {
if (!dcachePort->sendTimingReq(snd_data_pkt)) {
// The main packet will be deleted in completeDataAccess.
delete snd_data_pkt->req;

4
src/cpu/o3/lsq_unit_impl.hh
View File

@@ -1180,7 +1180,7 @@ template <class Impl>
bool
LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
{
if (!dcachePort->sendTiming(data_pkt)) {
if (!dcachePort->sendTimingReq(data_pkt)) {
// Need to handle becoming blocked on a store.
isStoreBlocked = true;
++lsqCacheBlocked;
@@ -1203,7 +1203,7 @@ LSQUnit<Impl>::recvRetry()
LSQSenderState *state =
dynamic_cast<LSQSenderState *>(retryPkt->senderState);
if (dcachePort->sendTiming(retryPkt)) {
if (dcachePort->sendTimingReq(retryPkt)) {
// Don't finish the store unless this is the last packet.
if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
state->pendingPacket == retryPkt) {

22
src/cpu/simple/timing.cc
View File

@@ -234,7 +234,7 @@ TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
new IprEvent(pkt, this, nextCycle(curTick() + delay));
_status = DcacheWaitResponse;
dcache_pkt = NULL;
} else if (!dcachePort.sendTiming(pkt)) {
} else if (!dcachePort.sendTimingReq(pkt)) {
_status = DcacheRetry;
dcache_pkt = pkt;
} else {
@@ -449,7 +449,7 @@ TimingSimpleCPU::handleWritePacket()
new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
_status = DcacheWaitResponse;
dcache_pkt = NULL;
} else if (!dcachePort.sendTiming(dcache_pkt)) {
} else if (!dcachePort.sendTimingReq(dcache_pkt)) {
_status = DcacheRetry;
} else {
_status = DcacheWaitResponse;
@@ -581,7 +581,7 @@ TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
ifetch_pkt->dataStatic(&inst);
DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
if (!icachePort.sendTiming(ifetch_pkt)) {
if (!icachePort.sendTimingReq(ifetch_pkt)) {
// Need to wait for retry
_status = IcacheRetry;
} else {
@@ -715,9 +715,8 @@ TimingSimpleCPU::IcachePort::ITickEvent::process()
}
bool
TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
{
assert(pkt->isResponse());
if (!pkt->wasNacked()) {
DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
// delay processing of returned data until next CPU clock edge
@@ -732,7 +731,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
} else {
assert(cpu->_status == IcacheWaitResponse);
pkt->reinitNacked();
if (!sendTiming(pkt)) {
if (!sendTimingReq(pkt)) {
cpu->_status = IcacheRetry;
cpu->ifetch_pkt = pkt;
}
@@ -749,7 +748,7 @@ TimingSimpleCPU::IcachePort::recvRetry()
assert(cpu->ifetch_pkt != NULL);
assert(cpu->_status == IcacheRetry);
PacketPtr tmp = cpu->ifetch_pkt;
if (sendTiming(tmp)) {
if (sendTimingReq(tmp)) {
cpu->_status = IcacheWaitResponse;
cpu->ifetch_pkt = NULL;
}
@@ -836,9 +835,8 @@ TimingSimpleCPU::completeDrain()
}
bool
TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
{
assert(pkt->isResponse());
if (!pkt->wasNacked()) {
// delay processing of returned data until next CPU clock edge
Tick next_tick = cpu->nextCycle(curTick());
@@ -862,7 +860,7 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
} else {
assert(cpu->_status == DcacheWaitResponse);
pkt->reinitNacked();
if (!sendTiming(pkt)) {
if (!sendTimingReq(pkt)) {
cpu->_status = DcacheRetry;
cpu->dcache_pkt = pkt;
}
@@ -896,7 +894,7 @@ TimingSimpleCPU::DcachePort::recvRetry()
dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
assert(main_send_state);
if (sendTiming(tmp)) {
if (sendTimingReq(tmp)) {
// If we were able to send without retrying, record that fact
// and try sending the other fragment.
send_state->clearFromParent();
@@ -914,7 +912,7 @@ TimingSimpleCPU::DcachePort::recvRetry()
cpu->dcache_pkt = NULL;
}
}
} else if (sendTiming(tmp)) {
} else if (sendTimingReq(tmp)) {
cpu->_status = DcacheWaitResponse;
// memory system takes ownership of packet
cpu->dcache_pkt = NULL;

6
src/cpu/simple/timing.hh
View File

@@ -156,7 +156,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
/**
* Snooping a coherence request, do nothing.
*/
virtual bool recvTimingSnoop(PacketPtr pkt) { return true; }
virtual void recvTimingSnoopReq(PacketPtr pkt) { }
TimingSimpleCPU* cpu;
@@ -185,7 +185,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
virtual bool recvTiming(PacketPtr pkt);
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvRetry();
@@ -212,7 +212,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
virtual bool recvTiming(PacketPtr pkt);
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvRetry();

2
src/cpu/testers/directedtest/InvalidateGenerator.cc
View File

@@ -80,7 +80,7 @@ InvalidateGenerator::initiate()
*dummyData = 0;
pkt->dataDynamic(dummyData);
if (port->sendTiming(pkt)) {
if (port->sendTimingReq(pkt)) {
DPRINTF(DirectedTest, "initiating request - successful\n");
if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
m_status = InvalidateGeneratorStatus_Load_Pending;

2
src/cpu/testers/directedtest/RubyDirectedTester.cc
View File

@@ -91,7 +91,7 @@ RubyDirectedTester::getMasterPort(const std::string &if_name, int idx)
}
bool
RubyDirectedTester::CpuPort::recvTiming(PacketPtr pkt)
RubyDirectedTester::CpuPort::recvTimingResp(PacketPtr pkt)
{
tester->hitCallback(id, pkt->getAddr());

2
src/cpu/testers/directedtest/RubyDirectedTester.hh
View File

@@ -59,7 +59,7 @@ class RubyDirectedTester : public MemObject
{}
protected:
virtual bool recvTiming(PacketPtr pkt);
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvRetry()
{ panic("%s does not expect a retry\n", name()); }
};

2
src/cpu/testers/directedtest/SeriesRequestGenerator.cc
View File

@@ -70,7 +70,7 @@ SeriesRequestGenerator::initiate()
*dummyData = 0;
pkt->dataDynamic(dummyData);
if (port->sendTiming(pkt)) {
if (port->sendTimingReq(pkt)) {
DPRINTF(DirectedTest, "initiating request - successful\n");
m_status = SeriesRequestGeneratorStatus_Request_Pending;
return true;

7
src/cpu/testers/memtest/memtest.cc
View File

@@ -53,9 +53,8 @@ using namespace std;
int TESTER_ALLOCATOR=0;
bool
MemTest::CpuPort::recvTiming(PacketPtr pkt)
MemTest::CpuPort::recvTimingResp(PacketPtr pkt)
{
assert(pkt->isResponse());
memtest->completeRequest(pkt);
return true;
}
@@ -72,7 +71,7 @@ MemTest::sendPkt(PacketPtr pkt) {
cachePort.sendAtomic(pkt);
completeRequest(pkt);
}
else if (!cachePort.sendTiming(pkt)) {
else if (!cachePort.sendTimingReq(pkt)) {
DPRINTF(MemTest, "accessRetry setting to true\n");
//
@@ -379,7 +378,7 @@ MemTest::tick()
void
MemTest::doRetry()
{
if (cachePort.sendTiming(retryPkt)) {
if (cachePort.sendTimingReq(retryPkt)) {
DPRINTF(MemTest, "accessRetry setting to false\n");
accessRetry = false;
retryPkt = NULL;

4
src/cpu/testers/memtest/memtest.hh
View File

@@ -97,9 +97,9 @@ class MemTest : public MemObject
protected:
virtual bool recvTiming(PacketPtr pkt);
virtual bool recvTimingResp(PacketPtr pkt);
virtual bool recvTimingSnoop(PacketPtr pkt) { return true; }
virtual void recvTimingSnoopReq(PacketPtr pkt) { }
virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }

7
src/cpu/testers/networktest/networktest.cc
View File

@@ -51,9 +51,8 @@ using namespace std;
int TESTER_NETWORK=0;
bool
NetworkTest::CpuPort::recvTiming(PacketPtr pkt)
NetworkTest::CpuPort::recvTimingResp(PacketPtr pkt)
{
assert(pkt->isResponse());
networktest->completeRequest(pkt);
return true;
}
@@ -67,7 +66,7 @@ NetworkTest::CpuPort::recvRetry()
void
NetworkTest::sendPkt(PacketPtr pkt)
{
if (!cachePort.sendTiming(pkt)) {
if (!cachePort.sendTimingReq(pkt)) {
retryPkt = pkt; // RubyPort will retry sending
}
numPacketsSent++;
@@ -269,7 +268,7 @@ NetworkTest::generatePkt()
void
NetworkTest::doRetry()
{
if (cachePort.sendTiming(retryPkt)) {
if (cachePort.sendTimingReq(retryPkt)) {
retryPkt = NULL;
}
}

2
src/cpu/testers/networktest/networktest.hh
View File

@@ -92,7 +92,7 @@ class NetworkTest : public MemObject
protected:
virtual bool recvTiming(PacketPtr pkt);
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvRetry();
};

8
src/cpu/testers/rubytest/Check.cc
View File

@@ -114,7 +114,7 @@ Check::initiatePrefetch()
pkt->senderState =
new SenderState(m_address, req->getSize(), pkt->senderState);
if (port->sendTiming(pkt)) {
if (port->sendTimingReq(pkt)) {
DPRINTF(RubyTest, "successfully initiated prefetch.\n");
} else {
// If the packet did not issue, must delete
@@ -154,7 +154,7 @@ Check::initiateFlush()
pkt->senderState =
new SenderState(m_address, req->getSize(), pkt->senderState);
if (port->sendTiming(pkt)) {
if (port->sendTimingReq(pkt)) {
DPRINTF(RubyTest, "initiating Flush - successful\n");
}
}
@@ -201,7 +201,7 @@ Check::initiateAction()
pkt->senderState =
new SenderState(writeAddr, req->getSize(), pkt->senderState);
if (port->sendTiming(pkt)) {
if (port->sendTimingReq(pkt)) {
DPRINTF(RubyTest, "initiating action - successful\n");
DPRINTF(RubyTest, "status before action update: %s\n",
(TesterStatus_to_string(m_status)).c_str());
@@ -253,7 +253,7 @@ Check::initiateCheck()
pkt->senderState =
new SenderState(m_address, req->getSize(), pkt->senderState);
if (port->sendTiming(pkt)) {
if (port->sendTimingReq(pkt)) {
DPRINTF(RubyTest, "initiating check - successful\n");
DPRINTF(RubyTest, "status before check update: %s\n",
TesterStatus_to_string(m_status).c_str());

2
src/cpu/testers/rubytest/RubyTester.cc
View File

@@ -145,7 +145,7 @@ RubyTester::getMasterPort(const std::string &if_name, int idx)
}
bool
RubyTester::CpuPort::recvTiming(PacketPtr pkt)
RubyTester::CpuPort::recvTimingResp(PacketPtr pkt)
{
// retrieve the subblock and call hitCallback
RubyTester::SenderState* senderState =

2
src/cpu/testers/rubytest/RubyTester.hh
View File

@@ -62,7 +62,7 @@ class RubyTester : public MemObject
{}
protected:
virtual bool recvTiming(PacketPtr pkt);
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvRetry()
{ panic("%s does not expect a retry\n", name()); }
};