diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 214b07236c..95be144988 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -216,10 +216,12 @@ class AbstractController : public ClockedObject, public Consumer */ template void incomingTransactionStart(Addr addr, - EventType type, StateType initialState) + EventType type, StateType initialState, bool retried) { assert(m_inTrans.find(addr) == m_inTrans.end()); m_inTrans[addr] = {type, initialState, curTick()}; + if (retried) + ++(*stats.inTransLatRetries[type]); } /** @@ -237,6 +239,7 @@ class AbstractController : public ClockedObject, public Consumer [iter->second.state] [(unsigned)finalState]->sample( ticksToCycles(curTick() - iter->second.time)); + ++(*stats.inTransLatTotal[iter->second.transaction]); m_inTrans.erase(iter); } @@ -260,12 +263,14 @@ class AbstractController : public ClockedObject, public Consumer * * @param addr address of the line with an outstanding transaction */ - void outgoingTransactionEnd(Addr addr) + void outgoingTransactionEnd(Addr addr, bool retried) { auto iter = m_outTrans.find(addr); assert(iter != m_outTrans.end()); stats.outTransLatHist[iter->second.transaction]->sample( ticksToCycles(curTick() - iter->second.time)); + if (retried) + ++(*stats.outTransLatHistRetries[iter->second.transaction]); m_outTrans.erase(iter); } @@ -356,10 +361,13 @@ class AbstractController : public ClockedObject, public Consumer // states. Only histograms with samples will appear in the stats std::vector>> inTransLatHist; + std::vector inTransLatRetries; + std::vector inTransLatTotal; // Initialized by the SLICC compiler for all events. // Only histograms with samples will appear in the stats. std::vector outTransLatHist; + std::vector outTransLatHistRetries; //! Counter for the number of cycles when the transitions carried out //! were equal to the maximum allowed diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 23f8707cb7..012441d99c 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -1,4 +1,4 @@ -# Copyright (c) 2019-2020 ARM Limited +# Copyright (c) 2019-2021 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -849,6 +849,7 @@ $c_ident::regStats() } } } + for (${ident}_Event event = ${ident}_Event_FIRST; event < ${ident}_Event_NUM; ++event) { std::string stat_name = @@ -858,9 +859,27 @@ $c_ident::regStats() t->init(5); t->flags(Stats::pdf | Stats::total | Stats::oneline | Stats::nozero); + + Stats::Scalar* r = new Stats::Scalar(&stats, + (stat_name + ".retries").c_str()); + stats.outTransLatHistRetries.push_back(r); + r->flags(Stats::nozero); } + for (${ident}_Event event = ${ident}_Event_FIRST; event < ${ident}_Event_NUM; ++event) { + std::string stat_name = ".inTransLatHist." + + ${ident}_Event_to_string(event); + Stats::Scalar* r = new Stats::Scalar(&stats, + (stat_name + ".total").c_str()); + stats.inTransLatTotal.push_back(r); + r->flags(Stats::nozero); + + r = new Stats::Scalar(&stats, + (stat_name + ".retries").c_str()); + stats.inTransLatRetries.push_back(r); + r->flags(Stats::nozero); + stats.inTransLatHist.emplace_back(); for (${ident}_State initial_state = ${ident}_State_FIRST; initial_state < ${ident}_State_NUM; ++initial_state) {