diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index d311d14573..3c94531ecc 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014,2018-2019 ARM Limited
+ * Copyright (c) 2013-2014,2018-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -48,6 +48,7 @@
 #include "debug/Activity.hh"
 #include "debug/Branch.hh"
 #include "debug/Drain.hh"
+#include "debug/ExecFaulting.hh"
 #include "debug/MinorExecute.hh"
 #include "debug/MinorInterrupt.hh"
 #include "debug/MinorMem.hh"
@@ -978,6 +979,15 @@ Execute::commitInst(MinorDynInstPtr inst, bool early_memory_issue,
         committed = true;
 
         if (fault != NoFault) {
+            if (inst->traceData) {
+                if (DTRACE(ExecFaulting)) {
+                    inst->traceData->setFaulting(true);
+                } else {
+                    delete inst->traceData;
+                    inst->traceData = NULL;
+                }
+            }
+
             DPRINTF(MinorExecute, "Fault in execute of inst: %s fault: %s\n",
                 *inst, fault->name());
             fault->invoke(thread, inst->staticInst);
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 667f42b2ee..4f467e96a6 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1,6 +1,6 @@
 /*
  * Copyright 2014 Google, Inc.
- * Copyright (c) 2010-2014, 2017 ARM Limited
+ * Copyright (c) 2010-2014, 2017, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1260,6 +1260,7 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
             tid, head_inst->seqNum);
         if (head_inst->traceData) {
             if (DTRACE(ExecFaulting)) {
+                head_inst->traceData->setFaulting(true);
                 head_inst->traceData->setFetchSeq(head_inst->seqNum);
                 head_inst->traceData->setCPSeq(thread[tid]->numOp);
                 head_inst->traceData->dump();
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4671402c91..c57fe14d22 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -1,6 +1,6 @@
 /*
  * Copyright 2014 Google, Inc.
- * Copyright (c) 2012-2013,2015,2017-2019 ARM Limited
+ * Copyright (c) 2012-2013,2015,2017-2020 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -713,10 +713,8 @@ AtomicSimpleCPU::tick()
                 if (fault == NoFault) {
                     countInst();
                     ppCommit->notify(std::make_pair(thread, curStaticInst));
-                }
-                else if (traceData && !DTRACE(ExecFaulting)) {
-                    delete traceData;
-                    traceData = NULL;
+                } else if (traceData) {
+                    traceFault();
                 }
 
                 if (fault != NoFault &&
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index c6d57616bb..1dac921f60 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, 2015, 2017, 2018 ARM Limited
+ * Copyright (c) 2010-2012, 2015, 2017, 2018, 2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -64,6 +64,7 @@
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Decode.hh"
+#include "debug/ExecFaulting.hh"
 #include "debug/Fetch.hh"
 #include "debug/Quiesce.hh"
 #include "mem/packet.hh"
@@ -432,6 +433,17 @@ BaseSimpleCPU::wakeup(ThreadID tid)
     }
 }
 
+void
+BaseSimpleCPU::traceFault()
+{
+    if (DTRACE(ExecFaulting)) {
+        traceData->setFaulting(true);
+    } else {
+        delete traceData;
+        traceData = NULL;
+    }
+}
+
 void
 BaseSimpleCPU::checkForInterrupts()
 {
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 323850ac51..9f5bf662b2 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012,2015,2018 ARM Limited
+ * Copyright (c) 2011-2012,2015,2018,2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -120,6 +120,14 @@ class BaseSimpleCPU : public BaseCPU
 
     Status _status;
 
+    /**
+     * Handler used when encountering a fault; its purpose is to
+     * tear down the InstRecord. If a fault is meant to be traced,
+     * the handler won't delete the record and it will annotate
+     * the record as coming from a faulting instruction.
+     */
+    void traceFault();
+
   public:
     void checkForInterrupts();
     void setupFetchRequest(const RequestPtr &req);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index c1c70cb381..84d7d0eb75 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1,6 +1,6 @@
 /*
  * Copyright 2014 Google, Inc.
- * Copyright (c) 2010-2013,2015,2017-2018 ARM Limited
+ * Copyright (c) 2010-2013,2015,2017-2018, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -363,10 +363,8 @@ TimingSimpleCPU::translationFault(const Fault &fault)
     updateCycleCounts();
     updateCycleCounters(BaseCPU::CPU_STATE_ON);
 
-    if (traceData) {
-        // Since there was a fault, we shouldn't trace this instruction.
-        delete traceData;
-        traceData = NULL;
+    if ((fault != NoFault) && traceData) {
+        traceFault();
     }
 
     postExecute();
@@ -794,9 +792,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
         // ifetch
         if (_status == BaseSimpleCPU::Running) {
             if (fault != NoFault && traceData) {
-                // If there was a fault, we shouldn't trace this instruction.
-                delete traceData;
-                traceData = NULL;
+                traceFault();
             }
 
             postExecute();
@@ -813,9 +809,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
         // keep an instruction count
         if (fault == NoFault)
             countInst();
-        else if (traceData && !DTRACE(ExecFaulting)) {
-            delete traceData;
-            traceData = NULL;
+        else if (traceData) {
+            traceFault();
         }
 
         postExecute();
@@ -913,9 +908,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
     if (fault == NoFault)
         countInst();
     else if (traceData) {
-        // If there was a fault, we shouldn't trace this instruction.
-        delete traceData;
-        traceData = NULL;
+        traceFault();
     }
 
     delete pkt;