From 3f8e97913464cb0487b1f6f8d0c3a390a06fee81 Mon Sep 17 00:00:00 2001
From: Matthew Poremba <matthew.poremba@amd.com>
Date: Tue, 22 Jun 2021 18:32:14 -0500
Subject: [PATCH] arch-vega: Simplify VecRegContainer in Vega

VecRegContainer was simplified in [1] while the Vega patches were still
under review so the changes in [1] were not applied to arch-vega.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/41995

Change-Id: I350ac94dc14e3ba0fb9619fa084e80cc8cbd7660
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47100
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/amdgpu/vega/gpu_registers.hh | 31 ++++-----------------------
 src/arch/amdgpu/vega/operand.hh       |  8 ++-----
 2 files changed, 6 insertions(+), 33 deletions(-)

diff --git a/src/arch/amdgpu/vega/gpu_registers.hh b/src/arch/amdgpu/vega/gpu_registers.hh
index 0d2f948b99..6118fb2910 100644
--- a/src/arch/amdgpu/vega/gpu_registers.hh
+++ b/src/arch/amdgpu/vega/gpu_registers.hh
@@ -174,33 +174,10 @@ namespace VegaISA
      */
     const int RegSizeDWords = sizeof(VecElemU32) / DWordSize;
 
-    // typedefs for the various sizes/types of vector regs
-    using VecRegU8 = ::VecRegT<VecElemU8, NumVecElemPerVecReg, false>;
-    using VecRegI8 = ::VecRegT<VecElemI8, NumVecElemPerVecReg, false>;
-    using VecRegU16 = ::VecRegT<VecElemU16, NumVecElemPerVecReg, false>;
-    using VecRegI16 = ::VecRegT<VecElemI16, NumVecElemPerVecReg, false>;
-    using VecRegU32 = ::VecRegT<VecElemU32, NumVecElemPerVecReg, false>;
-    using VecRegI32 = ::VecRegT<VecElemI32, NumVecElemPerVecReg, false>;
-    using VecRegF32 = ::VecRegT<VecElemF32, NumVecElemPerVecReg, false>;
-    using VecRegU64 = ::VecRegT<VecElemU64, NumVecElemPerVecReg, false>;
-    using VecRegI64 = ::VecRegT<VecElemI64, NumVecElemPerVecReg, false>;
-    using VecRegF64 = ::VecRegT<VecElemF64, NumVecElemPerVecReg, false>;
-    // non-writeable versions of vector regs
-    using ConstVecRegU8 = ::VecRegT<VecElemU8, NumVecElemPerVecReg, true>;
-    using ConstVecRegI8 = ::VecRegT<VecElemI8, NumVecElemPerVecReg, true>;
-    using ConstVecRegU16 = ::VecRegT<VecElemU16, NumVecElemPerVecReg, true>;
-    using ConstVecRegI16 = ::VecRegT<VecElemI16, NumVecElemPerVecReg, true>;
-    using ConstVecRegU32 = ::VecRegT<VecElemU32, NumVecElemPerVecReg, true>;
-    using ConstVecRegI32 = ::VecRegT<VecElemI32, NumVecElemPerVecReg, true>;
-    using ConstVecRegF32 = ::VecRegT<VecElemF32, NumVecElemPerVecReg, true>;
-    using ConstVecRegU64 = ::VecRegT<VecElemU64, NumVecElemPerVecReg, true>;
-    using ConstVecRegI64 = ::VecRegT<VecElemI64, NumVecElemPerVecReg, true>;
-    using ConstVecRegF64 = ::VecRegT<VecElemF64, NumVecElemPerVecReg, true>;
-
-    using VecRegContainerU8 = VecRegU8::Container;
-    using VecRegContainerU16 = VecRegU16::Container;
-    using VecRegContainerU32 = VecRegU32::Container;
-    using VecRegContainerU64 = VecRegU64::Container;
+    using VecRegContainerU32 =
+        VecRegContainer<sizeof(VecElemU32) * NumVecElemPerVecReg>;
+    using VecRegContainerU64 =
+        VecRegContainer<sizeof(VecElemU64) * NumVecElemPerVecReg>;
 
     struct StatusReg
     {
diff --git a/src/arch/amdgpu/vega/operand.hh b/src/arch/amdgpu/vega/operand.hh
index a4517ea054..bb89fb37fd 100644
--- a/src/arch/amdgpu/vega/operand.hh
+++ b/src/arch/amdgpu/vega/operand.hh
@@ -326,12 +326,8 @@ namespace VegaISA
               scRegData.read();
           }
 
-          using VecRegCont = typename std::conditional_t<NumDwords == 2,
-              VecRegContainerU64, typename std::conditional_t<sizeof(DataType)
-                  == sizeof(VecElemU16), VecRegContainerU16,
-                      typename std::conditional_t<sizeof(DataType)
-                          == sizeof(VecElemU8), VecRegContainerU8,
-                              VecRegContainerU32>>>;
+          using VecRegCont =
+              VecRegContainer<sizeof(DataType) * NumVecElemPerVecReg>;
 
           /**
            * whether this operand a scalar or not.