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CPU: Separate out native trace into ISA (in)dependent code and SimObjects.

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--HG--
rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc
rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh
rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
This commit is contained in:
Gabe Black
2009-07-19 23:54:56 -07:00
parent a3a795769a
commit 3e8e813218
12 changed files with 556 additions and 293 deletions
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6
src/cpu/SConscript
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@@ -112,6 +112,7 @@ SimObject('BaseCPU.py')
SimObject('FuncUnit.py')
SimObject('ExeTracer.py')
SimObject('IntelTrace.py')
SimObject('NativeTrace.py')
Source('activity.cc')
Source('base.cc')
@@ -119,6 +120,7 @@ Source('cpuevent.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
Source('nativetrace.cc')
Source('pc_event.cc')
Source('quiesce_event.cc')
Source('static_inst.cc')
@@ -136,10 +138,6 @@ if env['FULL_SYSTEM']:
SimObject('LegionTrace.py')
Source('legiontrace.cc')
if env['TARGET_ISA'] == 'x86':
SimObject('NativeTrace.py')
Source('nativetrace.cc')
if env['USE_CHECKER']:
Source('checker/cpu.cc')
TraceFlag('Checker')