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CPU: Separate out native trace into ISA (in)dependent code and SimObjects.

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--HG--
rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc
rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh
rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
This commit is contained in:
Gabe Black
2009-07-19 23:54:56 -07:00
parent a3a795769a
commit 3e8e813218
12 changed files with 556 additions and 293 deletions
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3
src/arch/sparc/SConscript
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@@ -35,11 +35,14 @@ if env['TARGET_ISA'] == 'sparc':
Source('asi.cc')
Source('faults.cc')
Source('isa.cc')
Source('nativetrace.cc')
Source('pagetable.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
Source('utility.cc')
SimObject('SparcNativeTrace.py')
SimObject('SparcTLB.py')
TraceFlag('Sparc', "Generic SPARC ISA stuff")
TraceFlag('RegisterWindows', "Register window manipulation")