system-arm: Add device tree for new VExpress GEM5_V2 platform
Change-Id: Ifc2b91afe5b88a656b4ed1c64ab6cca97f082034 Reviewed-on: https://gem5-review.googlesource.com/c/14275 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Jairo Balart
@@ -32,14 +32,23 @@ DTC?=dtc
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DTC_CPP_FLAGS=-nostdinc -undef
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TARGETS=\
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armv7_gem5_v1_1cpu.dtb armv7_gem5_v1_2cpu.dtb \
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armv7_gem5_v1_4cpu.dtb armv7_gem5_v1_8cpu.dtb \
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armv7_gem5_v1_1cpu.dtb \
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armv7_gem5_v1_2cpu.dtb \
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armv7_gem5_v1_4cpu.dtb \
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armv7_gem5_v1_8cpu.dtb \
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armv7_gem5_v1_16cpu.dtb \
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armv8_gem5_v1_1cpu.dtb armv8_gem5_v1_2cpu.dtb \
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armv8_gem5_v1_4cpu.dtb armv8_gem5_v1_8cpu.dtb \
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armv8_gem5_v1_1cpu.dtb \
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armv8_gem5_v1_2cpu.dtb \
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armv8_gem5_v1_4cpu.dtb \
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armv8_gem5_v1_8cpu.dtb \
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armv8_gem5_v1_16cpu.dtb \
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armv8_gem5_v1_big_little_2_2.dtb \
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armv8_gem5_v1_big_little_2_4.dtb
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armv8_gem5_v1_big_little_2_4.dtb \
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armv8_gem5_v2_1cpu.dtb \
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armv8_gem5_v2_2cpu.dtb \
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armv8_gem5_v2_4cpu.dtb \
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armv8_gem5_v2_8cpu.dtb \
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armv8_gem5_v2_16cpu.dtb
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GEN_DTS=mkdir -p .gen; \
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$(CPP) -x assembler-with-cpp \
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@@ -52,12 +61,17 @@ all: $(TARGETS)
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platforms/vexpress_gem5_v1.dtsi: platforms/vexpress_gem5_v1_base.dtsi
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platforms/vexpress_gem5_v2.dtsi: platforms/vexpress_gem5_v2_base.dtsi
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.gen/armv7_gem5_v1_%cpu.dts: armv7.dts platforms/vexpress_gem5_v1.dtsi
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$(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
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.gen/armv8_gem5_v1_%cpu.dts: armv8.dts platforms/vexpress_gem5_v1.dtsi
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$(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
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.gen/armv8_gem5_v2_%cpu.dts: armv8.dts platforms/vexpress_gem5_v2.dtsi
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$(call GEN_DTS,vexpress_gem5_v2.dtsi,$*)
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.gen/armv8_gem5_v1_big_little%.dts: armv8_big_little.dts \
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platforms/vexpress_gem5_v1.dtsi
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$(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
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46
system/arm/dt/platforms/vexpress_gem5_v2.dtsi
Normal file
46
system/arm/dt/platforms/vexpress_gem5_v2.dtsi
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@@ -0,0 +1,46 @@
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/*
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* Copyright (c) 2015-2018 ARM Limited
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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*/
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#include "vexpress_gem5_v2_base.dtsi"
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/ {
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/* The display processor needs custom configuration to setup its
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* output ports. Disable it by default in the platform until the
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* DT bindings have stabilize.
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*/
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dp0: hdlcd@2b000000 {
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compatible = "arm,hdlcd";
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reg = <0x0 0x2b000000 0x0 0x1000>;
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interrupts = <0 63 4>;
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clocks = <&osc_pxl>;
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clock-names = "pxlclk";
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status = "disabled";
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};
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};
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193
system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
Normal file
193
system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
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@@ -0,0 +1,193 @@
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/*
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* Copyright (c) 2015-2017 ARM Limited
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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*/
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/ {
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arm,hbi = <0x0>;
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arm,vexpress,site = <0xf>;
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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gic: interrupt-controller@2c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <0x3>;
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#address-cells = <0x2>;
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interrupt-controller;
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redistributor-stride = <0x0 0x40000>; // 256kB stride, needed for ARM AVS tests...
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reg = <0x0 0x2c000000 0x0 0x10000
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0x0 0x2c010000 0x0 0x4000000 // room for 256 redistributors using 128K each (256K strided...)
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0x0 0x0 0x0 0x0>;
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interrupts = <1 9 0xf04>;
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#size-cells = <0x2>;
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linux,phandle = <0x1>;
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phandle = <0x1>;
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};
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>;
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clocks = <&osc_sys>;
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clock-names="apb_pclk";
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};
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pci {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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#address-cells = <0x3>;
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#size-cells = <0x2>;
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#interrupt-cells = <0x1>;
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reg = <0x0 0x30000000 0x0 0x10000000>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>,
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<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
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/*
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child unit address, #cells = #address-cells
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child interrupt specifier, #cells = #interrupt-cells (INTA = 1, INTB = 2, INTC = 3 and INTD = 4)
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interrupt-parent, phandle
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parent unit address, #cells = #address-cells@gic
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parent interrupt specifier, #cells = #interrupt-cells@gic
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*/
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x44 0x1
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0x800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x45 0x1
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0x1000 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x46 0x1
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0x1800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x47 0x1>;
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interrupt-map-mask = <0x001800 0x0 0x0 0x0>;
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dma-coherent;
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};
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kmi@1c060000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x1c060000 0x0 0x1000>;
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interrupts = <0 12 4>;
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clocks = <&v2m_clk24mhz>, <&osc_smb>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@1c070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x1c070000 0x0 0x1000>;
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interrupts = <0 13 4>;
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clocks = <&v2m_clk24mhz>, <&osc_smb>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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uart0: uart@1c090000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x1c090000 0x0 0x1000>;
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interrupts = <0 5 4>;
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clocks = <&osc_peripheral>, <&osc_smb>;
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clock-names = "uartclk", "apb_pclk";
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};
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rtc@1c170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x0 0x1c170000 0x0 0x1000>;
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interrupts = <0 4 4>;
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clocks = <&osc_smb>;
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clock-names = "apb_pclk";
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};
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v2m_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "v2m:clk24mhz";
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};
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v2m_sysreg: sysreg@1c010000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0 0x1c010000 0x0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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vio@1c130000 {
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compatible = "virtio,mmio";
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reg = <0 0x1c130000 0x0 0x1000>;
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interrupts = <0 42 4>;
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};
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vio@1c140000 {
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compatible = "virtio,mmio";
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reg = <0 0x1c140000 0x0 0x1000>;
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interrupts = <0 43 4>;
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};
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dcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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osc_pxl: osc@5 {
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 5>;
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freq-range = <23750000 1000000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk5";
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};
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osc_smb: osc@6 {
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 6>;
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freq-range = <20000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk6";
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};
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osc_sys: osc@7 {
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 7>;
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freq-range = <20000000 60000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk7";
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};
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};
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mcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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arm,vexpress,site = <0>;
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osc_peripheral: osc@2 {
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 2>;
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freq-range = <24000000 24000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk2";
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};
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};
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};
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