derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch: Make the ISA class inherit from SimObject

Browse Source 
The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
This commit is contained in:
Andreas Sandberg
2013-01-07 13:05:35 -05:00
parent 69d419f313
commit 3db3f83a5e
46 changed files with 611 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
src/cpu/BaseCPU.py
View File

@@ -57,21 +57,33 @@ default_tracer = ExeTracer()
if buildEnv['TARGET_ISA'] == 'alpha':
from AlphaTLB import AlphaDTB, AlphaITB
from AlphaInterrupts import AlphaInterrupts
from AlphaISA import AlphaISA
isa_class = AlphaISA
elif buildEnv['TARGET_ISA'] == 'sparc':
from SparcTLB import SparcTLB
from SparcInterrupts import SparcInterrupts
from SparcISA import SparcISA
isa_class = SparcISA
elif buildEnv['TARGET_ISA'] == 'x86':
from X86TLB import X86TLB
from X86LocalApic import X86LocalApic
from X86ISA import X86ISA
isa_class = X86ISA
elif buildEnv['TARGET_ISA'] == 'mips':
from MipsTLB import MipsTLB
from MipsInterrupts import MipsInterrupts
from MipsISA import MipsISA
isa_class = MipsISA
elif buildEnv['TARGET_ISA'] == 'arm':
from ArmTLB import ArmTLB
from ArmInterrupts import ArmInterrupts
from ArmISA import ArmISA
isa_class = ArmISA
elif buildEnv['TARGET_ISA'] == 'power':
from PowerTLB import PowerTLB
from PowerInterrupts import PowerInterrupts
from PowerISA import PowerISA
isa_class = PowerISA
class BaseCPU(MemObject):
type = 'BaseCPU'
@@ -113,31 +125,37 @@ class BaseCPU(MemObject):
itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
interrupts = Param.SparcInterrupts(
NULL, "Interrupt Controller")
isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'alpha':
dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
interrupts = Param.AlphaInterrupts(
NULL, "Interrupt Controller")
isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'x86':
dtb = Param.X86TLB(X86TLB(), "Data TLB")
itb = Param.X86TLB(X86TLB(), "Instruction TLB")
interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'mips':
dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
interrupts = Param.MipsInterrupts(
NULL, "Interrupt Controller")
isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'arm':
dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
interrupts = Param.ArmInterrupts(
NULL, "Interrupt Controller")
isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'power':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
interrupts = Param.PowerInterrupts(
NULL, "Interrupt Controller")
isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
else:
print "Don't know what TLB to use for ISA %s" % \
buildEnv['TARGET_ISA']
@@ -241,5 +259,10 @@ class BaseCPU(MemObject):
self.toL2Bus.master = self.l2cache.cpu_side
self._cached_ports = ['l2cache.mem_side']
def createThreads(self):
self.isa = [ isa_class() for i in xrange(self.numThreads) ]
if self.checker != NULL:
self.checker.createThreads()
def addCheckerCpu(self):
pass

5
src/cpu/base.cc
View File

@@ -230,6 +230,11 @@ BaseCPU::BaseCPU(Params *p, bool is_checker)
profileEvent = new ProfileEvent(this, params()->profile);
}
tracer = params()->tracer;
if (params()->isa.size() != numThreads) {
fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
"of threads (%i).\n", params()->isa.size(), numThreads);
}
}
void

7
src/cpu/checker/cpu.cc
View File

@@ -96,14 +96,17 @@ CheckerCPU::~CheckerCPU()
void
CheckerCPU::setSystem(System *system)
{
const Params *p(dynamic_cast<const Params *>(_params));
systemPtr = system;
if (FullSystem) {
thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
p->isa[0], false);
} else {
thread = new SimpleThread(this, 0, systemPtr,
workload.size() ? workload[0] : NULL,
itb, dtb);
itb, dtb, p->isa[0]);
}
tc = thread->getTC();

1
src/cpu/dummy_checker.cc
View File

@@ -69,6 +69,7 @@ DummyCheckerParams::create()
params->itb = itb;
params->dtb = dtb;
params->isa = isa;
params->system = system;
params->cpu_id = cpu_id;
params->profile = profile;

16
src/cpu/inorder/cpu.cc
View File

@@ -230,6 +230,7 @@ InOrderCPU::InOrderCPU(Params *params)
tickEvent(this),
stageWidth(params->stageWidth),
resPool(new ResourcePool(this, params)),
isa(numThreads, NULL),
timeBuffer(2 , 2),
dataPort(resPool->getDataUnit(), ".dcache_port"),
instPort(resPool->getInstUnit(), ".icache_port"),
@@ -280,6 +281,7 @@ InOrderCPU::InOrderCPU(Params *params)
}
for (ThreadID tid = 0; tid < numThreads; ++tid) {
isa[tid] = params->isa[tid];
pc[tid].set(0);
lastCommittedPC[tid].set(0);
@@ -358,7 +360,7 @@ InOrderCPU::InOrderCPU(Params *params)
memset(intRegs[tid], 0, sizeof(intRegs[tid]));
memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
isa[tid].clear();
isa[tid]->clear();
// Define dummy instructions and resource requests to be used.
dummyInst[tid] = new InOrderDynInst(this,
@@ -1249,11 +1251,11 @@ InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
{
if (reg_idx < FP_Base_DepTag) {
reg_type = IntType;
return isa[tid].flattenIntIndex(reg_idx);
return isa[tid]->flattenIntIndex(reg_idx);
} else if (reg_idx < Ctrl_Base_DepTag) {
reg_type = FloatType;
reg_idx -= FP_Base_DepTag;
return isa[tid].flattenFloatIndex(reg_idx);
return isa[tid]->flattenFloatIndex(reg_idx);
} else {
reg_type = MiscType;
return reg_idx - TheISA::Ctrl_Base_DepTag;
@@ -1369,25 +1371,25 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
MiscReg
InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
{
return isa[tid].readMiscRegNoEffect(misc_reg);
return isa[tid]->readMiscRegNoEffect(misc_reg);
}
MiscReg
InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
{
return isa[tid].readMiscReg(misc_reg, tcBase(tid));
return isa[tid]->readMiscReg(misc_reg, tcBase(tid));
}
void
InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
{
isa[tid].setMiscRegNoEffect(misc_reg, val);
isa[tid]->setMiscRegNoEffect(misc_reg, val);
}
void
InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
{
isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
}

2
src/cpu/inorder/cpu.hh
View File

@@ -325,7 +325,7 @@ class InOrderCPU : public BaseCPU
TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
/** ISA state */
TheISA::ISA isa[ThePipeline::MaxThreads];
std::vector<TheISA::ISA *> isa;
/** Dependency Tracker for Integer & Floating Point Regs */
RegDepMap archRegDepMap[ThePipeline::MaxThreads];

14
src/cpu/inorder/thread_context.cc
View File

@@ -173,7 +173,7 @@ InOrderThreadContext::copyArchRegs(ThreadContext *src_tc)
void
InOrderThreadContext::clearArchRegs()
{
cpu->isa[thread->threadId()].clear();
cpu->isa[thread->threadId()]->clear();
}
@@ -181,7 +181,7 @@ uint64_t
InOrderThreadContext::readIntReg(int reg_idx)
{
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenIntIndex(reg_idx);
reg_idx = cpu->isa[tid]->flattenIntIndex(reg_idx);
return cpu->readIntReg(reg_idx, tid);
}
@@ -189,7 +189,7 @@ FloatReg
InOrderThreadContext::readFloatReg(int reg_idx)
{
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
return cpu->readFloatReg(reg_idx, tid);
}
@@ -197,7 +197,7 @@ FloatRegBits
InOrderThreadContext::readFloatRegBits(int reg_idx)
{
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
return cpu->readFloatRegBits(reg_idx, tid);
}
@@ -211,7 +211,7 @@ void
InOrderThreadContext::setIntReg(int reg_idx, uint64_t val)
{
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenIntIndex(reg_idx);
reg_idx = cpu->isa[tid]->flattenIntIndex(reg_idx);
cpu->setIntReg(reg_idx, val, tid);
}
@@ -219,7 +219,7 @@ void
InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val)
{
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
cpu->setFloatReg(reg_idx, val, tid);
}
@@ -227,7 +227,7 @@ void
InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val)
{
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
cpu->setFloatRegBits(reg_idx, val, tid);
}

4
src/cpu/inorder/thread_context.hh
View File

@@ -254,10 +254,10 @@ class InOrderThreadContext : public ThreadContext
void setMiscReg(int misc_reg, const MiscReg &val);
int flattenIntIndex(int reg)
{ return cpu->isa[thread->threadId()].flattenIntIndex(reg); }
{ return cpu->isa[thread->threadId()]->flattenIntIndex(reg); }
int flattenFloatIndex(int reg)
{ return cpu->isa[thread->threadId()].flattenFloatIndex(reg); }
{ return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); }
void activateContext(Cycles delay)
{ cpu->activateContext(thread->threadId(), delay); }

1
src/cpu/o3/checker.cc
View File

@@ -82,6 +82,7 @@ O3CheckerParams::create()
params->itb = itb;
params->dtb = dtb;
params->isa = isa;
params->system = system;
params->cpu_id = cpu_id;
params->profile = profile;

12
src/cpu/o3/cpu.cc
View File

@@ -241,6 +241,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
TheISA::NumMiscRegs * numThreads,
TheISA::ZeroReg),
isa(numThreads, NULL),
icachePort(&fetch, this),
dcachePort(&iew.ldstQueue, this),
@@ -340,6 +342,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
for (ThreadID tid = 0; tid < numThreads; tid++) {
bool bindRegs = (tid <= active_threads - 1);
isa[tid] = params->isa[tid];
commitRenameMap[tid].init(TheISA::NumIntRegs,
params->numPhysIntRegs,
lreg_idx, //Index for Logical. Regs
@@ -1285,7 +1289,7 @@ template <class Impl>
TheISA::MiscReg
FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
{
return this->isa[tid].readMiscRegNoEffect(misc_reg);
return this->isa[tid]->readMiscRegNoEffect(misc_reg);
}
template <class Impl>
@@ -1293,7 +1297,7 @@ TheISA::MiscReg
FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
{
miscRegfileReads++;
return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
}
template <class Impl>
@@ -1301,7 +1305,7 @@ void
FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
const TheISA::MiscReg &val, ThreadID tid)
{
this->isa[tid].setMiscRegNoEffect(misc_reg, val);
this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
}
template <class Impl>
@@ -1310,7 +1314,7 @@ FullO3CPU<Impl>::setMiscReg(int misc_reg,
const TheISA::MiscReg &val, ThreadID tid)
{
miscRegfileWrites++;
this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
}
template <class Impl>

2
src/cpu/o3/cpu.hh
View File

@@ -634,7 +634,7 @@ class FullO3CPU : public BaseO3CPU
/** Integer Register Scoreboard */
Scoreboard scoreboard;
TheISA::ISA isa[Impl::MaxThreads];
std::vector<TheISA::ISA *> isa;
/** Instruction port. Note that it has to appear after the fetch stage. */
IcachePort icachePort;

18
src/cpu/o3/thread_context_impl.hh
View File

@@ -219,14 +219,14 @@ template <class Impl>
void
O3ThreadContext<Impl>::clearArchRegs()
{
cpu->isa[thread->threadId()].clear();
cpu->isa[thread->threadId()]->clear();
}
template <class Impl>
uint64_t
O3ThreadContext<Impl>::readIntReg(int reg_idx)
{
reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
reg_idx = cpu->isa[thread->threadId()]->flattenIntIndex(reg_idx);
return cpu->readArchIntReg(reg_idx, thread->threadId());
}
@@ -234,7 +234,7 @@ template <class Impl>
TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx)
{
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
return cpu->readArchFloatReg(reg_idx, thread->threadId());
}
@@ -242,7 +242,7 @@ template <class Impl>
TheISA::FloatRegBits
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
{
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
}
@@ -250,7 +250,7 @@ template <class Impl>
void
O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
{
reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
reg_idx = cpu->isa[thread->threadId()]->flattenIntIndex(reg_idx);
cpu->setArchIntReg(reg_idx, val, thread->threadId());
conditionalSquash();
@@ -260,7 +260,7 @@ template <class Impl>
void
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
{
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
cpu->setArchFloatReg(reg_idx, val, thread->threadId());
conditionalSquash();
@@ -270,7 +270,7 @@ template <class Impl>
void
O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
{
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
conditionalSquash();
@@ -298,14 +298,14 @@ template <class Impl>
int
O3ThreadContext<Impl>::flattenIntIndex(int reg)
{
return cpu->isa[thread->threadId()].flattenIntIndex(reg);
return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
}
template <class Impl>
int
O3ThreadContext<Impl>::flattenFloatIndex(int reg)
{
return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
}
template <class Impl>

1
src/cpu/ozone/checker_builder.cc
View File

@@ -89,6 +89,7 @@ OzoneCheckerParams::create()
params->itb = itb;
params->dtb = dtb;
params->isa = isa;
params->system = system;
params->cpu_id = cpu_id;
params->profile = profile;

1
src/cpu/ozone/cpu_builder.cc
View File

@@ -80,6 +80,7 @@ DerivOzoneCPUParams::create()
params->itb = itb;
params->dtb = dtb;
params->isa = isa;
params->system = system;
params->cpu_id = cpu_id;

1
src/cpu/ozone/simple_cpu_builder.cc
View File

@@ -83,6 +83,7 @@ SimpleOzoneCPUParams::create()
params->itb = itb;
params->dtb = dtb;
params->isa = isa;
params->system = system;
params->cpu_id = cpu_id;

5
src/cpu/simple/base.cc
View File

@@ -87,10 +87,11 @@ BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
: BaseCPU(p), traceData(NULL), thread(NULL)
{
if (FullSystem)
thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
p->isa[0]);
else
thread = new SimpleThread(this, /* thread_num */ 0, p->system,
p->workload[0], p->itb, p->dtb);
p->workload[0], p->itb, p->dtb, p->isa[0]);
thread->setStatus(ThreadContext::Halted);

17
src/cpu/simple_thread.cc
View File

@@ -61,9 +61,9 @@ using namespace std;
// constructor
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
Process *_process, TheISA::TLB *_itb,
TheISA::TLB *_dtb)
: ThreadState(_cpu, _thread_num, _process), system(_sys), itb(_itb),
dtb(_dtb)
TheISA::TLB *_dtb, TheISA::ISA *_isa)
: ThreadState(_cpu, _thread_num, _process), isa(_isa), system(_sys),
itb(_itb), dtb(_dtb)
{
clearArchRegs();
tc = new ProxyThreadContext<SimpleThread>(this);
@@ -71,8 +71,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
TheISA::TLB *_itb, TheISA::TLB *_dtb,
bool use_kernel_stats)
: ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb)
TheISA::ISA *_isa, bool use_kernel_stats)
: ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
dtb(_dtb)
{
tc = new ProxyThreadContext<SimpleThread>(this);
@@ -99,7 +100,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
}
SimpleThread::SimpleThread()
: ThreadState(NULL, -1, NULL)
: ThreadState(NULL, -1, NULL), isa(NULL)
{
tc = new ProxyThreadContext<SimpleThread>(this);
}
@@ -182,7 +183,7 @@ SimpleThread::serialize(ostream &os)
//
// Now must serialize all the ISA dependent state
//
isa.serialize(baseCpu, os);
isa->serialize(baseCpu, os);
}
@@ -198,7 +199,7 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
//
// Now must unserialize all the ISA dependent state
//
isa.unserialize(baseCpu, cp, section);
isa->unserialize(baseCpu, cp, section);
}
void

33
src/cpu/simple_thread.hh
View File

@@ -108,7 +108,7 @@ class SimpleThread : public ThreadState
FloatRegBits i[TheISA::NumFloatRegs];
} floatRegs;
TheISA::IntReg intRegs[TheISA::NumIntRegs];
TheISA::ISA isa; // one "instance" of the current ISA.
TheISA::ISA *const isa; // one "instance" of the current ISA.
TheISA::PCState _pcState;
@@ -133,11 +133,12 @@ class SimpleThread : public ThreadState
// constructor: initialize SimpleThread from given process structure
// FS
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
TheISA::TLB *_itb, TheISA::TLB *_dtb,
TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
bool use_kernel_stats = true);
// SE
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb);
Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
TheISA::ISA *_isa);
SimpleThread();
@@ -226,7 +227,7 @@ class SimpleThread : public ThreadState
_pcState = 0;
memset(intRegs, 0, sizeof(intRegs));
memset(floatRegs.i, 0, sizeof(floatRegs.i));
isa.clear();
isa->clear();
}
//
@@ -234,7 +235,7 @@ class SimpleThread : public ThreadState
//
uint64_t readIntReg(int reg_idx)
{
int flatIndex = isa.flattenIntIndex(reg_idx);
int flatIndex = isa->flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
uint64_t regVal = intRegs[flatIndex];
DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
@@ -244,7 +245,7 @@ class SimpleThread : public ThreadState
FloatReg readFloatReg(int reg_idx)
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
FloatReg regVal = floatRegs.f[flatIndex];
DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
@@ -254,7 +255,7 @@ class SimpleThread : public ThreadState
FloatRegBits readFloatRegBits(int reg_idx)
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
FloatRegBits regVal = floatRegs.i[flatIndex];
DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
@@ -264,7 +265,7 @@ class SimpleThread : public ThreadState
void setIntReg(int reg_idx, uint64_t val)
{
int flatIndex = isa.flattenIntIndex(reg_idx);
int flatIndex = isa->flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
reg_idx, flatIndex, val);
@@ -273,7 +274,7 @@ class SimpleThread : public ThreadState
void setFloatReg(int reg_idx, FloatReg val)
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
floatRegs.f[flatIndex] = val;
DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
@@ -282,7 +283,7 @@ class SimpleThread : public ThreadState
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
// XXX: Fix array out of bounds compiler error for gem5.fast
// when checkercpu enabled
@@ -341,37 +342,37 @@ class SimpleThread : public ThreadState
MiscReg
readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
{
return isa.readMiscRegNoEffect(misc_reg);
return isa->readMiscRegNoEffect(misc_reg);
}
MiscReg
readMiscReg(int misc_reg, ThreadID tid = 0)
{
return isa.readMiscReg(misc_reg, tc);
return isa->readMiscReg(misc_reg, tc);
}
void
setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
{
return isa.setMiscRegNoEffect(misc_reg, val);
return isa->setMiscRegNoEffect(misc_reg, val);
}
void
setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
{
return isa.setMiscReg(misc_reg, val, tc);
return isa->setMiscReg(misc_reg, val, tc);
}
int
flattenIntIndex(int reg)
{
return isa.flattenIntIndex(reg);
return isa->flattenIntIndex(reg);
}
int
flattenFloatIndex(int reg)
{
return isa.flattenFloatIndex(reg);
return isa->flattenFloatIndex(reg);
}
unsigned readStCondFailures() { return storeCondFailures; }