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Added ULL for 64bit ints

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Added function to skip determine_cpu_caches(). We may have to update this in the
future: see note below.

arch/alpha/alpha_memory.cc:
dev/ide_ctrl.cc:
dev/tsunamireg.h:
    Added ULL for 64bit ints
kern/linux/linux_system.cc:
    Added a function to skip determine_cpu_caches, right now it is only used for
    printing in proc, however in the future we may either want to implement the SC_CTL
    IPR register or manually set alpha_l1i_cacheshape, alpha_l1d_cacheshape,
    alpha_l2_cacheshape, alpha_l3_cacheshape to ((size << 10) | (linesize>>1)<<4 | way)
kern/linux/linux_system.hh:
    added event to skip determine_cpu_caches()

--HG--
extra : convert_revision : 1065f2091bbe6832b730af490f5b4672c2afedce
This commit is contained in:
Ali Saidi
2004-05-09 20:14:18 -04:00
parent 4a5dcc37bf
commit 3c7071a6be
5 changed files with 18 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
dev/ide_ctrl.cc
View File

@@ -291,7 +291,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
pioInterface->addAddrRange(pri_cmd_addr,
pri_cmd_addr + pri_cmd_size - 1);
pri_cmd_addr = ((pri_cmd_addr | 0xf0000000000) & PA_IMPL_MASK);
pri_cmd_addr = ((pri_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
break;
case PCI0_BASE_ADDR1:
@@ -300,7 +300,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
pioInterface->addAddrRange(pri_ctrl_addr,
pri_ctrl_addr + pri_ctrl_size - 1);
pri_ctrl_addr = ((pri_ctrl_addr | 0xf0000000000) & PA_IMPL_MASK);
pri_ctrl_addr = ((pri_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
break;
case PCI0_BASE_ADDR2:
@@ -309,7 +309,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
pioInterface->addAddrRange(sec_cmd_addr,
sec_cmd_addr + sec_cmd_size - 1);
sec_cmd_addr = ((sec_cmd_addr | 0xf0000000000) & PA_IMPL_MASK);
sec_cmd_addr = ((sec_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
break;
case PCI0_BASE_ADDR3:
@@ -318,7 +318,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
pioInterface->addAddrRange(sec_ctrl_addr,
sec_ctrl_addr + sec_ctrl_size - 1);
sec_ctrl_addr = ((sec_ctrl_addr | 0xf0000000000) & PA_IMPL_MASK);
sec_ctrl_addr = ((sec_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
break;
case PCI0_BASE_ADDR4:
@@ -326,7 +326,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
if (pioInterface)
pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
bmi_addr = ((bmi_addr | 0xf0000000000) & PA_IMPL_MASK);
bmi_addr = ((bmi_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
break;
}
}