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cpu,arch-arm: Initialise data members

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The value that is not initialized has a bogus value that manifests when
using some debug-flags what makes the usage of tracediff a bit more
challenging.

In addition, while debugging with other techniques, it introduces the
problem of understanding if the value of a field is 'intended' or just
an effect of the lack of initialisation.

Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13125
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Rekai Gonzalez-Alberquilla
2017-02-10 17:30:22 +00:00
committed by Giacomo Gabrielli
parent c918d1435c
commit 3bb49cb2b0
11 changed files with 65 additions and 16 deletions
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12
src/cpu/o3/commit_impl.hh
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@@ -132,17 +132,19 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
"RoundRobin, OldestReady");
}
for (ThreadID tid = 0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
commitStatus[tid] = Idle;
changedROBNumEntries[tid] = false;
checkEmptyROB[tid] = false;
trapInFlight[tid] = false;
committedStores[tid] = false;
trapSquash[tid] = false;
tcSquash[tid] = false;
squashAfterInst[tid] = nullptr;
pc[tid].set(0);
youngestSeqNum[tid] = 0;
lastCommitedSeqNum[tid] = 0;
squashAfterInst[tid] = NULL;
trapInFlight[tid] = false;
committedStores[tid] = false;
checkEmptyROB[tid] = false;
renameMap[tid] = nullptr;
}
interrupt = NoFault;
}