diff --git a/src/arch/riscv/gdb-xml/riscv-32bit-csr.xml b/src/arch/riscv/gdb-xml/riscv-32bit-csr.xml
index 7cf7bc05b4..4e5d3e64e9 100644
--- a/src/arch/riscv/gdb-xml/riscv-32bit-csr.xml
+++ b/src/arch/riscv/gdb-xml/riscv-32bit-csr.xml
@@ -32,6 +32,7 @@
   <reg name="stval" bitsize="32"/>
   <reg name="sip" bitsize="32"/>
   <reg name="satp" bitsize="32"/>
+  <reg name="senvcfg" bitsize="32"/>
   <reg name="mvendorid" bitsize="32"/>
   <reg name="marchid" bitsize="32"/>
   <reg name="mimpid" bitsize="32"/>
diff --git a/src/arch/riscv/gdb-xml/riscv-64bit-csr.xml b/src/arch/riscv/gdb-xml/riscv-64bit-csr.xml
index 3c9d2e90f4..7028c09279 100644
--- a/src/arch/riscv/gdb-xml/riscv-64bit-csr.xml
+++ b/src/arch/riscv/gdb-xml/riscv-64bit-csr.xml
@@ -30,6 +30,7 @@
   <reg name="stval" bitsize="64"/>
   <reg name="sip" bitsize="64"/>
   <reg name="satp" bitsize="64"/>
+  <reg name="senvcfg" bitsize="64"/>
   <reg name="mvendorid" bitsize="64"/>
   <reg name="marchid" bitsize="64"/>
   <reg name="mimpid" bitsize="64"/>
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 7f4d97f4e9..54499610da 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -185,6 +185,7 @@ namespace RiscvISA
     [MISCREG_SCAUSE]        = "SCAUSE",
     [MISCREG_STVAL]         = "STVAL",
     [MISCREG_SATP]          = "SATP",
+    [MISCREG_SENVCFG]       = "SENVCFG",
 
     [MISCREG_UTVEC]         = "UTVEC",
     [MISCREG_USCRATCH]      = "USCRATCH",
@@ -779,6 +780,11 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                 setMiscRegNoEffect(idx, new_val);
             }
             break;
+          case MISCREG_SENVCFG:
+            {
+                setMiscRegNoEffect(idx, val + 1);
+            }
+            break;
           case MISCREG_TSELECT:
             {
                 // we don't support debugging, so always set a different value
diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index 9985c20364..64c656f3c4 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -183,6 +183,7 @@ enum MiscRegIndex
     MISCREG_SCAUSE,
     MISCREG_STVAL,
     MISCREG_SATP,
+    MISCREG_SENVCFG,
 
     MISCREG_UTVEC,
     MISCREG_USCRATCH,
@@ -360,6 +361,7 @@ enum CSRIndex
     CSR_STVAL = 0x143,
     CSR_SIP = 0x144,
     CSR_SATP = 0x180,
+    CSR_SENVCFG = 0x10A, // 20240411 RISCV spec, volume 2
 
     CSR_MVENDORID = 0xF11,
     CSR_MARCHID = 0xF12,
@@ -777,6 +779,9 @@ const std::unordered_map<int, CSRMetadata> CSRData = {
         {"sip", MISCREG_SIP, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
     {CSR_SATP,
         {"satp", MISCREG_SATP, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
+    {CSR_SENVCFG,
+        {"senvcfg", MISCREG_SENVCFG, rvTypeFlags(RV64, RV32),
+         isaExtsFlags('s')}},
 
     {CSR_MVENDORID,
         {"mvendorid", MISCREG_VENDORID, rvTypeFlags(RV64, RV32),
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 3cd1f9d76c..7948a745b5 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -327,6 +327,8 @@ RemoteGDB::Riscv32GdbRegCache::getRegs(ThreadContext *context)
         CSRData.at(CSR_SIP).physIndex) & RVxCSRMasks.at(CSR_SIP);
     r.satp = context->readMiscRegNoEffect(
         CSRData.at(CSR_SATP).physIndex);
+    r.senvcfg = context->readMiscRegNoEffect(
+        CSRData.at(CSR_SENVCFG).physIndex);
 
     // M mode CSR
     r.mvendorid = context->readMiscRegNoEffect(
@@ -426,6 +428,8 @@ RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const
         CSRData.at(CSR_STVAL).physIndex, r.stval);
     context->setMiscRegNoEffect(
         CSRData.at(CSR_SATP).physIndex, r.satp);
+    context->setMiscRegNoEffect(
+        CSRData.at(CSR_SENVCFG).physIndex, r.senvcfg);
 
     // M mode CSR
     setRegWithMask(context, RV32, pms, CSR_MSTATUS, r.mstatus);
@@ -528,6 +532,8 @@ RemoteGDB::Riscv64GdbRegCache::getRegs(ThreadContext *context)
         CSRData.at(CSR_SIP).physIndex) & RVxCSRMasks.at(CSR_SIP);
     r.satp = context->readMiscRegNoEffect(
         CSRData.at(CSR_SATP).physIndex);
+    r.senvcfg = context->readMiscRegNoEffect(
+        CSRData.at(CSR_SENVCFG).physIndex);
 
     // M mode CSR
     r.mvendorid = context->readMiscRegNoEffect(
@@ -625,7 +631,8 @@ RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const
         CSRData.at(CSR_STVAL).physIndex, r.stval);
     context->setMiscRegNoEffect(
         CSRData.at(CSR_SATP).physIndex, r.satp);
-
+    context->setMiscRegNoEffect(
+        CSRData.at(CSR_SENVCFG).physIndex, r.senvcfg);
     // M mode CSR
     setRegWithMask(context, RV64, pms, CSR_MSTATUS, r.mstatus);
     setRegNoEffectWithMask(context, RV64, pms, CSR_MISA, r.misa);
diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index 2afe3e9553..36bf7d1b8c 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -108,6 +108,7 @@ class RemoteGDB : public BaseRemoteGDB
             uint32_t stval;
             uint32_t sip;
             uint32_t satp;
+            uint32_t senvcfg;
             uint32_t mvendorid;
             uint32_t marchid;
             uint32_t mimpid;
@@ -192,6 +193,7 @@ class RemoteGDB : public BaseRemoteGDB
             uint64_t stval;
             uint64_t sip;
             uint64_t satp;
+            uint64_t senvcfg;
             uint64_t mvendorid;
             uint64_t marchid;
             uint64_t mimpid;