From 3b4f241fb5a05f29e2235d0dea33475ebbbc3185 Mon Sep 17 00:00:00 2001
From: Roger Chang <rogerycchang@google.com>
Date: Tue, 17 Jan 2023 10:38:11 +0800
Subject: [PATCH] arch-riscv: Fix incorrect trap value of instruction fault

As we add rv_type bit in machInst at 62, It will get the machine
code with rv_type specification if we just return machInst. We
only need return machine code for handling instruction fault.

Change-Id: I9dd7a25047d4a13df5b47dc9e422345ba44b7b09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67677
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/riscv/faults.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index e66476727c..f687fd6f20 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -173,7 +173,7 @@ class InstFault : public RiscvFault
         : RiscvFault(n, FaultType::OTHERS, INST_ILLEGAL), _inst(inst)
     {}
 
-    RegVal trap_value() const override { return _inst; }
+    RegVal trap_value() const override { return bits(_inst, 31, 0); }
 };
 
 class UnknownInstFault : public InstFault