derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Make CPU models use new LoadLockedReq/StoreCondReq commands.

Browse Source 
--HG--
extra : convert_revision : ab78d9d1d88c3698edfd653d71c8882e1272b781
This commit is contained in:
Steve Reinhardt
2007-06-30 20:35:42 -07:00
parent 5e59739416
commit 3ad761bc8e
6 changed files with 56 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
src/cpu/simple/atomic.cc
View File

@@ -280,7 +280,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
// Now do the access.
if (fault == NoFault) {
Packet pkt = Packet(req, MemCmd::ReadReq, Packet::Broadcast);
Packet pkt =
Packet(req,
req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
Packet::Broadcast);
pkt.dataStatic(&data);
if (req->isMmapedIpr())
@@ -370,23 +373,24 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
// Now do the access.
if (fault == NoFault) {
Packet pkt =
Packet(req, req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq,
Packet::Broadcast);
pkt.dataStatic(&data);
MemCmd cmd = MemCmd::WriteReq; // default
bool do_access = true; // flag to suppress cache access
if (req->isLocked()) {
cmd = MemCmd::StoreCondReq;
do_access = TheISA::handleLockedWrite(thread, req);
} else if (req->isSwap()) {
cmd = MemCmd::SwapReq;
if (req->isCondSwap()) {
assert(res);
req->setExtraData(*res);
}
}
if (req->isCondSwap()) {
assert(res);
req->setExtraData(*res);
}
if (do_access) {
Packet pkt = Packet(req, cmd, Packet::Broadcast);
pkt.dataStatic(&data);
if (req->isMmapedIpr()) {
dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
} else {
@@ -395,12 +399,14 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
}
dcache_access = true;
assert(!pkt.isError());
if (req->isSwap()) {
assert(res);
*res = pkt.get<T>();
}
}
if (req->isSwap()) {
assert(res);
*res = pkt.get<T>();
} else if (res) {
if (res && !req->isSwap()) {
*res = req->getExtraData();
}
}

33
src/cpu/simple/timing.cc
View File

@@ -260,7 +260,10 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
// Now do the access.
if (fault == NoFault) {
PacketPtr pkt =
new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
new Packet(req,
(req->isLocked() ?
MemCmd::LoadLockedReq : MemCmd::ReadReq),
Packet::Broadcast);
pkt->dataDynamic<T>(new T);
if (!dcachePort.sendTiming(pkt)) {
@@ -350,25 +353,27 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
// Now do the access.
if (fault == NoFault) {
assert(dcache_pkt == NULL);
if (req->isSwap())
dcache_pkt = new Packet(req, MemCmd::SwapReq, Packet::Broadcast);
else
dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
dcache_pkt->allocate();
dcache_pkt->set(data);
MemCmd cmd = MemCmd::WriteReq; // default
bool do_access = true; // flag to suppress cache access
assert(dcache_pkt == NULL);
if (req->isLocked()) {
cmd = MemCmd::StoreCondReq;
do_access = TheISA::handleLockedWrite(thread, req);
}
if (req->isCondSwap()) {
assert(res);
req->setExtraData(*res);
} else if (req->isSwap()) {
cmd = MemCmd::SwapReq;
if (req->isCondSwap()) {
assert(res);
req->setExtraData(*res);
}
}
if (do_access) {
dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
dcache_pkt->allocate();
dcache_pkt->set(data);
if (!dcachePort.sendTiming(dcache_pkt)) {
_status = DcacheRetry;
} else {
@@ -609,7 +614,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
if (pkt->isRead() && pkt->req->isLocked()) {
if (pkt->isRead() && pkt->isLocked()) {
TheISA::handleLockedRead(thread, pkt->req);
}