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style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs

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This commit is contained in:
Ali Saidi
2008-09-10 14:26:15 -04:00
parent 09a8fb0b52
commit 3a3e356f4e
125 changed files with 2209 additions and 2209 deletions
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34
src/dev/alpha/access.h
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@@ -45,31 +45,31 @@ typedef unsigned long uint64_t;
// This structure hacked up from simos
struct AlphaAccess
{
uint32_t last_offset; // 00: must be first field
uint32_t version; // 04:
uint32_t numCPUs; // 08:
uint32_t intrClockFrequency; // 0C: Hz
uint64_t cpuClock; // 10: MHz
uint64_t mem_size; // 18:
uint32_t last_offset; // 00: must be first field
uint32_t version; // 04:
uint32_t numCPUs; // 08:
uint32_t intrClockFrequency; // 0C: Hz
uint64_t cpuClock; // 10: MHz
uint64_t mem_size; // 18:
// Loaded kernel
uint64_t kernStart; // 20:
uint64_t kernEnd; // 28:
uint64_t entryPoint; // 30:
uint64_t kernStart; // 20:
uint64_t kernEnd; // 28:
uint64_t entryPoint; // 30:
// console disk stuff
uint64_t diskUnit; // 38:
uint64_t diskCount; // 40:
uint64_t diskPAddr; // 48:
uint64_t diskBlock; // 50:
uint64_t diskOperation; // 58:
uint64_t diskUnit; // 38:
uint64_t diskCount; // 40:
uint64_t diskPAddr; // 48:
uint64_t diskBlock; // 50:
uint64_t diskOperation; // 58:
// console simple output stuff
uint64_t outputChar; // 60: Placeholder for output
uint64_t inputChar; // 68: Placeholder for input
uint64_t outputChar; // 60: Placeholder for output
uint64_t inputChar; // 68: Placeholder for input
// MP boot
uint64_t cpuStack[64]; // 70:
uint64_t cpuStack[64]; // 70:
};
#endif // __ALPHA_ACCESS_H__

20
src/dev/etherdump.cc
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@@ -50,26 +50,26 @@ EtherDump::EtherDump(const Params *p)
{
}
#define DLT_EN10MB 1 // Ethernet (10Mb)
#define TCPDUMP_MAGIC 0xa1b2c3d4
#define PCAP_VERSION_MAJOR 2
#define PCAP_VERSION_MINOR 4
#define DLT_EN10MB 1 // Ethernet (10Mb)
#define TCPDUMP_MAGIC 0xa1b2c3d4
#define PCAP_VERSION_MAJOR 2
#define PCAP_VERSION_MINOR 4
struct pcap_file_header {
uint32_t magic;
uint16_t version_major;
uint16_t version_minor;
int32_t thiszone; // gmt to local correction
uint32_t sigfigs; // accuracy of timestamps
uint32_t snaplen; // max length saved portion of each pkt
uint32_t linktype; // data link type (DLT_*)
int32_t thiszone; // gmt to local correction
uint32_t sigfigs; // accuracy of timestamps
uint32_t snaplen; // max length saved portion of each pkt
uint32_t linktype; // data link type (DLT_*)
};
struct pcap_pkthdr {
uint32_t seconds;
uint32_t microseconds;
uint32_t caplen; // length of portion present
uint32_t len; // length this packet (off wire)
uint32_t caplen; // length of portion present
uint32_t len; // length this packet (off wire)
};
void

34
src/dev/mips/access.h
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@@ -48,37 +48,37 @@ typedef unsigned long uint64_t;
// This structure hacked up from simos
struct MipsAccess
{
uint32_t inputChar; // 00: Placeholder for input
uint32_t last_offset; // 04: must be first field
uint32_t version; // 08:
uint32_t numCPUs; // 0C:
uint32_t intrClockFrequency; // 10: Hz
uint32_t inputChar; // 00: Placeholder for input
uint32_t last_offset; // 04: must be first field
uint32_t version; // 08:
uint32_t numCPUs; // 0C:
uint32_t intrClockFrequency; // 10: Hz
// Loaded kernel
uint32_t kernStart; // 14:
uint32_t kernEnd; // 18:
uint32_t entryPoint; // 1c:
uint32_t kernStart; // 14:
uint32_t kernEnd; // 18:
uint32_t entryPoint; // 1c:
// console simple output stuff
uint32_t outputChar; // 20: Placeholder for output
uint32_t outputChar; // 20: Placeholder for output
// console disk stuff
uint32_t diskUnit; // 24:
uint32_t diskCount; // 28:
uint32_t diskPAddr; // 2c:
uint32_t diskBlock; // 30:
uint32_t diskOperation; // 34:
uint32_t diskUnit; // 24:
uint32_t diskCount; // 28:
uint32_t diskPAddr; // 2c:
uint32_t diskBlock; // 30:
uint32_t diskOperation; // 34:
// MP boot
uint32_t cpuStack[64]; // 70:
uint32_t cpuStack[64]; // 70:
/* XXX There appears to be a problem in accessing
* unit64_t in the console.c file. They are treated
* like uint32_int and result in the wrong address for
* everything below. This problem should be investigated.
*/
uint64_t cpuClock; // 38: MHz
uint64_t mem_size; // 40:
uint64_t cpuClock; // 38: MHz
uint64_t mem_size; // 40:
};
#endif // __MIPS_ACCESS_H__

8
src/dev/ns_gige.hh
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@@ -62,10 +62,10 @@ const uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
* Ethernet device registers
*/
struct dp_regs {
uint32_t command;
uint32_t config;
uint32_t mear;
uint32_t ptscr;
uint32_t command;
uint32_t config;
uint32_t mear;
uint32_t ptscr;
uint32_t isr;
uint32_t imr;
uint32_t ier;

2
src/dev/pcidev.cc
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@@ -41,7 +41,7 @@
#include "base/inifile.hh"
#include "base/intmath.hh" // for isPowerOf2(
#include "base/misc.hh"
#include "base/str.hh" // for to_number
#include "base/str.hh" // for to_number
#include "base/trace.hh"
#include "dev/pciconfigall.hh"
#include "dev/pcidev.hh"

120
src/dev/pcireg.h
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@@ -69,18 +69,18 @@ union PCIConfig {
};
// Common PCI offsets
#define PCI_VENDOR_ID 0x00 // Vendor ID ro
#define PCI_DEVICE_ID 0x02 // Device ID ro
#define PCI_COMMAND 0x04 // Command rw
#define PCI_STATUS 0x06 // Status rw
#define PCI_REVISION_ID 0x08 // Revision ID ro
#define PCI_CLASS_CODE 0x09 // Class Code ro
#define PCI_SUB_CLASS_CODE 0x0A // Sub Class Code ro
#define PCI_BASE_CLASS_CODE 0x0B // Base Class Code ro
#define PCI_CACHE_LINE_SIZE 0x0C // Cache Line Size ro+
#define PCI_LATENCY_TIMER 0x0D // Latency Timer ro+
#define PCI_HEADER_TYPE 0x0E // Header Type ro
#define PCI_BIST 0x0F // Built in self test rw
#define PCI_VENDOR_ID 0x00 // Vendor ID ro
#define PCI_DEVICE_ID 0x02 // Device ID ro
#define PCI_COMMAND 0x04 // Command rw
#define PCI_STATUS 0x06 // Status rw
#define PCI_REVISION_ID 0x08 // Revision ID ro
#define PCI_CLASS_CODE 0x09 // Class Code ro
#define PCI_SUB_CLASS_CODE 0x0A // Sub Class Code ro
#define PCI_BASE_CLASS_CODE 0x0B // Base Class Code ro
#define PCI_CACHE_LINE_SIZE 0x0C // Cache Line Size ro+
#define PCI_LATENCY_TIMER 0x0D // Latency Timer ro+
#define PCI_HEADER_TYPE 0x0E // Header Type ro
#define PCI_BIST 0x0F // Built in self test rw
// some pci command reg bitfields
#define PCI_CMD_BME 0x04 // Bus master function enable
@@ -88,62 +88,62 @@ union PCIConfig {
#define PCI_CMD_IOSE 0x01 // I/O space enable
// Type 0 PCI offsets
#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw
#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw
#define PCI0_BASE_ADDR2 0x18 // Base Address 2 rw
#define PCI0_BASE_ADDR3 0x1C // Base Address 3 rw
#define PCI0_BASE_ADDR4 0x20 // Base Address 4 rw
#define PCI0_BASE_ADDR5 0x24 // Base Address 5 rw
#define PCI0_CIS 0x28 // CardBus CIS Pointer ro
#define PCI0_SUB_VENDOR_ID 0x2C // Sub-Vendor ID ro
#define PCI0_SUB_SYSTEM_ID 0x2E // Sub-System ID ro
#define PCI0_ROM_BASE_ADDR 0x30 // Expansion ROM Base Address rw
#define PCI0_RESERVED0 0x34
#define PCI0_RESERVED1 0x38
#define PCI0_INTERRUPT_LINE 0x3C // Interrupt Line rw
#define PCI0_INTERRUPT_PIN 0x3D // Interrupt Pin ro
#define PCI0_MINIMUM_GRANT 0x3E // Maximum Grant ro
#define PCI0_MAXIMUM_LATENCY 0x3F // Maximum Latency ro
#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw
#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw
#define PCI0_BASE_ADDR2 0x18 // Base Address 2 rw
#define PCI0_BASE_ADDR3 0x1C // Base Address 3 rw
#define PCI0_BASE_ADDR4 0x20 // Base Address 4 rw
#define PCI0_BASE_ADDR5 0x24 // Base Address 5 rw
#define PCI0_CIS 0x28 // CardBus CIS Pointer ro
#define PCI0_SUB_VENDOR_ID 0x2C // Sub-Vendor ID ro
#define PCI0_SUB_SYSTEM_ID 0x2E // Sub-System ID ro
#define PCI0_ROM_BASE_ADDR 0x30 // Expansion ROM Base Address rw
#define PCI0_RESERVED0 0x34
#define PCI0_RESERVED1 0x38
#define PCI0_INTERRUPT_LINE 0x3C // Interrupt Line rw
#define PCI0_INTERRUPT_PIN 0x3D // Interrupt Pin ro
#define PCI0_MINIMUM_GRANT 0x3E // Maximum Grant ro
#define PCI0_MAXIMUM_LATENCY 0x3F // Maximum Latency ro
// Type 1 PCI offsets
#define PCI1_BASE_ADDR0 0x10 // Base Address 0 rw
#define PCI1_BASE_ADDR1 0x14 // Base Address 1 rw
#define PCI1_PRI_BUS_NUM 0x18 // Primary Bus Number rw
#define PCI1_SEC_BUS_NUM 0x19 // Secondary Bus Number rw
#define PCI1_SUB_BUS_NUM 0x1A // Subordinate Bus Number rw
#define PCI1_SEC_LAT_TIMER 0x1B // Secondary Latency Timer ro+
#define PCI1_IO_BASE 0x1C // I/O Base rw
#define PCI1_IO_LIMIT 0x1D // I/O Limit rw
#define PCI1_SECONDARY_STATUS 0x1E // Secondary Status rw
#define PCI1_MEM_BASE 0x20 // Memory Base rw
#define PCI1_MEM_LIMIT 0x22 // Memory Limit rw
#define PCI1_PRF_MEM_BASE 0x24 // Prefetchable Memory Base rw
#define PCI1_PRF_MEM_LIMIT 0x26 // Prefetchable Memory Limit rw
#define PCI1_PRF_BASE_UPPER 0x28 // Prefetchable Base Upper 32 rw
#define PCI1_PRF_LIMIT_UPPER 0x2C // Prefetchable Limit Upper 32 rw
#define PCI1_IO_BASE_UPPER 0x30 // I/O Base Upper 16 bits rw
#define PCI1_IO_LIMIT_UPPER 0x32 // I/O Limit Upper 16 bits rw
#define PCI1_RESERVED 0x34 // Reserved ro
#define PCI1_ROM_BASE_ADDR 0x38 // Expansion ROM Base Address rw
#define PCI1_INTR_LINE 0x3C // Interrupt Line rw
#define PCI1_INTR_PIN 0x3D // Interrupt Pin ro
#define PCI1_BRIDGE_CTRL 0x3E // Bridge Control rw
#define PCI1_BASE_ADDR0 0x10 // Base Address 0 rw
#define PCI1_BASE_ADDR1 0x14 // Base Address 1 rw
#define PCI1_PRI_BUS_NUM 0x18 // Primary Bus Number rw
#define PCI1_SEC_BUS_NUM 0x19 // Secondary Bus Number rw
#define PCI1_SUB_BUS_NUM 0x1A // Subordinate Bus Number rw
#define PCI1_SEC_LAT_TIMER 0x1B // Secondary Latency Timer ro+
#define PCI1_IO_BASE 0x1C // I/O Base rw
#define PCI1_IO_LIMIT 0x1D // I/O Limit rw
#define PCI1_SECONDARY_STATUS 0x1E // Secondary Status rw
#define PCI1_MEM_BASE 0x20 // Memory Base rw
#define PCI1_MEM_LIMIT 0x22 // Memory Limit rw
#define PCI1_PRF_MEM_BASE 0x24 // Prefetchable Memory Base rw
#define PCI1_PRF_MEM_LIMIT 0x26 // Prefetchable Memory Limit rw
#define PCI1_PRF_BASE_UPPER 0x28 // Prefetchable Base Upper 32 rw
#define PCI1_PRF_LIMIT_UPPER 0x2C // Prefetchable Limit Upper 32 rw
#define PCI1_IO_BASE_UPPER 0x30 // I/O Base Upper 16 bits rw
#define PCI1_IO_LIMIT_UPPER 0x32 // I/O Limit Upper 16 bits rw
#define PCI1_RESERVED 0x34 // Reserved ro
#define PCI1_ROM_BASE_ADDR 0x38 // Expansion ROM Base Address rw
#define PCI1_INTR_LINE 0x3C // Interrupt Line rw
#define PCI1_INTR_PIN 0x3D // Interrupt Pin ro
#define PCI1_BRIDGE_CTRL 0x3E // Bridge Control rw
// Device specific offsets
#define PCI_DEVICE_SPECIFIC 0x40 // 192 bytes
#define PCI_DEVICE_SPECIFIC 0x40 // 192 bytes
#define PCI_CONFIG_SIZE 0xFF
// Some Vendor IDs
#define PCI_VENDOR_DEC 0x1011
#define PCI_VENDOR_NCR 0x101A
#define PCI_VENDOR_QLOGIC 0x1077
#define PCI_VENDOR_SIMOS 0x1291
#define PCI_VENDOR_DEC 0x1011
#define PCI_VENDOR_NCR 0x101A
#define PCI_VENDOR_QLOGIC 0x1077
#define PCI_VENDOR_SIMOS 0x1291
// Some Product IDs
#define PCI_PRODUCT_DEC_PZA 0x0008
#define PCI_PRODUCT_NCR_810 0x0001
#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
#define PCI_PRODUCT_SIMOS_SIMOS 0x1291
#define PCI_PRODUCT_SIMOS_ETHER 0x1292
#define PCI_PRODUCT_DEC_PZA 0x0008
#define PCI_PRODUCT_NCR_810 0x0001
#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
#define PCI_PRODUCT_SIMOS_SIMOS 0x1291
#define PCI_PRODUCT_SIMOS_ETHER 0x1292
#endif // __PCIREG_H__

2
src/dev/sinicreg.hh
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@@ -48,7 +48,7 @@
static const uint64_t NAME##_width = WIDTH; \
static const uint64_t NAME##_offset = OFFSET; \
static const uint64_t NAME##_mask = (ULL(1) << WIDTH) - 1; \
static const uint64_t NAME = ((ULL(1) << WIDTH) - 1) << OFFSET; \
static const uint64_t NAME = ((ULL(1) << WIDTH) - 1) << OFFSET; \
static inline uint64_t get_##NAME(uint64_t reg) \
{ return (reg & NAME) >> OFFSET; } \
static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \