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style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs

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This commit is contained in:
Ali Saidi
2008-09-10 14:26:15 -04:00
parent 09a8fb0b52
commit 3a3e356f4e
125 changed files with 2209 additions and 2209 deletions
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30
src/cpu/base_dyn_inst.hh
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@@ -77,8 +77,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
typedef typename std::list<DynInstPtr>::iterator ListIt;
enum {
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
};
/** The StaticInst used by this BaseDynInst. */
@@ -486,24 +486,24 @@ class BaseDynInst : public FastAlloc, public RefCounted
//
// Instruction types. Forward checks to StaticInst object.
//
bool isNop() const { return staticInst->isNop(); }
bool isMemRef() const { return staticInst->isMemRef(); }
bool isLoad() const { return staticInst->isLoad(); }
bool isStore() const { return staticInst->isStore(); }
bool isNop() const { return staticInst->isNop(); }
bool isMemRef() const { return staticInst->isMemRef(); }
bool isLoad() const { return staticInst->isLoad(); }
bool isStore() const { return staticInst->isStore(); }
bool isStoreConditional() const
{ return staticInst->isStoreConditional(); }
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
bool isCopy() const { return staticInst->isCopy(); }
bool isInteger() const { return staticInst->isInteger(); }
bool isFloating() const { return staticInst->isFloating(); }
bool isControl() const { return staticInst->isControl(); }
bool isCall() const { return staticInst->isCall(); }
bool isReturn() const { return staticInst->isReturn(); }
bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
bool isInteger() const { return staticInst->isInteger(); }
bool isFloating() const { return staticInst->isFloating(); }
bool isControl() const { return staticInst->isControl(); }
bool isCall() const { return staticInst->isCall(); }
bool isReturn() const { return staticInst->isReturn(); }
bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
bool isCondCtrl() const { return staticInst->isCondCtrl(); }
bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
bool isCondCtrl() const { return staticInst->isCondCtrl(); }
bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
bool isThreadSync() const { return staticInst->isThreadSync(); }
bool isSerializing() const { return staticInst->isSerializing(); }
@@ -560,7 +560,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
Addr branchTarget() const { return staticInst->branchTarget(PC); }
/** Returns the number of source registers. */
int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
/** Returns the number of destination registers. */
int8_t numDestRegs() const { return staticInst->numDestRegs(); }

2
src/cpu/checker/cpu.hh
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@@ -180,7 +180,7 @@ class CheckerCPU : public BaseCPU
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
void prefetch(Addr addr, unsigned flags)
{

4
src/cpu/checker/cpu_impl.hh
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@@ -141,9 +141,9 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
// Try to fetch the instruction
#if FULL_SYSTEM
#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
#else
#define IFETCH_FLAGS(pc) 0
#define IFETCH_FLAGS(pc) 0
#endif
uint64_t fetch_PC = thread->readPC() & ~3;

14
src/cpu/memtest/memtest.hh
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@@ -133,10 +133,10 @@ class MemTest : public MemObject
bool accessRetry;
unsigned size; // size of testing memory region
unsigned size; // size of testing memory region
unsigned percentReads; // target percentage of read accesses
unsigned percentFunctional; // target percentage of functional accesses
unsigned percentReads; // target percentage of read accesses
unsigned percentFunctional; // target percentage of functional accesses
unsigned percentUncacheable;
int id;
@@ -154,12 +154,12 @@ class MemTest : public MemObject
Addr traceBlockAddr;
Addr baseAddr1; // fix this to option
Addr baseAddr2; // fix this to option
Addr baseAddr1; // fix this to option
Addr baseAddr2; // fix this to option
Addr uncacheAddr;
unsigned progressInterval; // frequency of progress reports
Tick nextProgressMessage; // access # for next progress report
unsigned progressInterval; // frequency of progress reports
Tick nextProgressMessage; // access # for next progress report
unsigned percentSourceUnaligned;
unsigned percentDestUnaligned;

4
src/cpu/o3/alpha/dyn_inst.hh
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@@ -67,8 +67,8 @@ class AlphaDynInst : public BaseDynInst<Impl>
typedef TheISA::MiscReg MiscReg;
enum {
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
};
public:

4
src/cpu/o3/mips/dyn_inst.hh
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@@ -64,8 +64,8 @@ class MipsDynInst : public BaseDynInst<Impl>
typedef TheISA::MiscReg MiscReg;
enum {
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
};
public:

2
src/cpu/o3/regfile.hh
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@@ -265,7 +265,7 @@ class PhysRegFile
#if FULL_SYSTEM
private:
int intrflag; // interrupt flag
int intrflag; // interrupt flag
#endif
private:

10
src/cpu/ozone/back_end.hh
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@@ -447,7 +447,7 @@ class BackEnd
Stats::Scalar<> ROB_fcount;
Stats::Formula ROB_full_rate;
Stats::Vector<> ROB_count; // cumulative ROB occupancy
Stats::Vector<> ROB_count; // cumulative ROB occupancy
Stats::Formula ROB_occ_rate;
Stats::VectorDistribution<> ROB_occ_dist;
public:
@@ -482,8 +482,8 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
// unscheduleTickEvent();
// status = DcacheMissStall;
// unscheduleTickEvent();
// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
} else {
// do functional access
@@ -524,8 +524,8 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
if (result != MA_HIT && dcacheInterface->doEvents()) {
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
// unscheduleTickEvent();
// status = DcacheMissStall;
// unscheduleTickEvent();
// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
}
}

2
src/cpu/ozone/cpu_impl.hh
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@@ -585,7 +585,7 @@ OzoneCPU<Impl>::post_interrupt(int int_num, int index)
if (_status == Idle) {
DPRINTF(IPI,"Suspended Processor awoke\n");
// thread.activate();
// thread.activate();
// Hack for now. Otherwise might have to go through the tc, or
// I need to figure out what's the right thing to call.
activateContext(thread.readTid(), 1);

2
src/cpu/ozone/front_end.hh
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@@ -307,7 +307,7 @@ class FrontEnd
Stats::Formula idleRate;
Stats::Formula branchRate;
Stats::Formula fetchRate;
Stats::Scalar<> IFQCount; // cumulative IFQ occupancy
Stats::Scalar<> IFQCount; // cumulative IFQ occupancy
Stats::Formula IFQOccupancy;
Stats::Formula IFQLatency;
Stats::Scalar<> IFQFcount; // cumulative IFQ full count

10
src/cpu/ozone/inorder_back_end.hh
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@@ -222,7 +222,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
// are executed twice.
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
// unscheduleTickEvent();
// unscheduleTickEvent();
status = DcacheMissLoadStall;
DPRINTF(IBE, "Dcache miss stall!\n");
} else {
@@ -249,7 +249,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
if (fault == NoFault && dcacheInterface) {
memReq->cmd = Write;
// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
memReq->completionEvent = NULL;
memReq->time = curTick;
memReq->flags &= ~INST_READ;
@@ -261,7 +261,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
if (result != MA_HIT) {
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
// unscheduleTickEvent();
// unscheduleTickEvent();
status = DcacheMissStoreStall;
DPRINTF(IBE, "Dcache miss stall!\n");
} else {
@@ -307,7 +307,7 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
if (result != MA_HIT) {
req->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
// unscheduleTickEvent();
// unscheduleTickEvent();
status = DcacheMissLoadStall;
DPRINTF(IBE, "Dcache miss load stall!\n");
} else {
@@ -372,7 +372,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
if (result != MA_HIT) {
req->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
// unscheduleTickEvent();
// unscheduleTickEvent();
status = DcacheMissStoreStall;
DPRINTF(IBE, "Dcache miss store stall!\n");
} else {

2
src/cpu/ozone/lsq_unit_impl.hh
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@@ -553,7 +553,7 @@ OzoneLSQ<Impl>::writebackStores()
MemReqPtr req = storeQueue[storeWBIdx].req;
storeQueue[storeWBIdx].committed = true;
// Fault fault = cpu->translateDataReadReq(req);
// Fault fault = cpu->translateDataReadReq(req);
req->cmd = Write;
req->completionEvent = NULL;
req->time = curTick;

2
src/cpu/ozone/lw_back_end.hh
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@@ -407,7 +407,7 @@ class LWBackEnd
Stats::Scalar<> ROBFcount;
Stats::Formula ROBFullRate;
Stats::Vector<> ROBCount; // cumulative ROB occupancy
Stats::Vector<> ROBCount; // cumulative ROB occupancy
Stats::Formula ROBOccRate;
// Stats::VectorDistribution<> ROBOccDist;
public:

2
src/cpu/simple/base.hh
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@@ -227,7 +227,7 @@ class BaseSimpleCPU : public BaseCPU
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
M5_DUMMY_RETURN}
void prefetch(Addr addr, unsigned flags)

4
src/cpu/simple_thread.cc
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@@ -220,8 +220,8 @@ SimpleThread::activate(int delay)
lastActivate = curTick;
// if (status() == ThreadContext::Unallocated) {
// cpu->activateWhenReady(tid);
// return;
// cpu->activateWhenReady(tid);
// return;
// }
_status = ThreadContext::Active;

2
src/cpu/simple_thread.hh
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@@ -99,7 +99,7 @@ class SimpleThread : public ThreadState
typedef ThreadContext::Status Status;
protected:
RegFile regs; // correct-path register context
RegFile regs; // correct-path register context
public:
// pointer to CPU associated with this SimpleThread

78
src/cpu/static_inst.hh
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@@ -105,38 +105,38 @@ class StaticInstBase : public RefCounted
/// implement this behavior via the execute() methods.
///
enum Flags {
IsNop, ///< Is a no-op (no effect at all).
IsNop, ///< Is a no-op (no effect at all).
IsInteger, ///< References integer regs.
IsFloating, ///< References FP regs.
IsInteger, ///< References integer regs.
IsFloating, ///< References FP regs.
IsMemRef, ///< References memory (load, store, or prefetch).
IsLoad, ///< Reads from memory (load or prefetch).
IsStore, ///< Writes to memory.
IsMemRef, ///< References memory (load, store, or prefetch).
IsLoad, ///< Reads from memory (load or prefetch).
IsStore, ///< Writes to memory.
IsStoreConditional, ///< Store conditional instruction.
IsIndexed, ///< Accesses memory with an indexed address computation
IsInstPrefetch, ///< Instruction-cache prefetch.
IsDataPrefetch, ///< Data-cache prefetch.
IsInstPrefetch, ///< Instruction-cache prefetch.
IsDataPrefetch, ///< Data-cache prefetch.
IsCopy, ///< Fast Cache block copy
IsControl, ///< Control transfer instruction.
IsDirectControl, ///< PC relative control transfer.
IsIndirectControl, ///< Register indirect control transfer.
IsCondControl, ///< Conditional control transfer.
IsUncondControl, ///< Unconditional control transfer.
IsCall, ///< Subroutine call.
IsReturn, ///< Subroutine return.
IsControl, ///< Control transfer instruction.
IsDirectControl, ///< PC relative control transfer.
IsIndirectControl, ///< Register indirect control transfer.
IsCondControl, ///< Conditional control transfer.
IsUncondControl, ///< Unconditional control transfer.
IsCall, ///< Subroutine call.
IsReturn, ///< Subroutine return.
IsCondDelaySlot,///< Conditional Delay-Slot Instruction
IsThreadSync, ///< Thread synchronization operation.
IsThreadSync, ///< Thread synchronization operation.
IsSerializing, ///< Serializes pipeline: won't execute until all
IsSerializing, ///< Serializes pipeline: won't execute until all
/// older instructions have committed.
IsSerializeBefore,
IsSerializeAfter,
IsMemBarrier, ///< Is a memory barrier
IsWriteBarrier, ///< Is a write barrier
IsMemBarrier, ///< Is a memory barrier
IsWriteBarrier, ///< Is a write barrier
IsERET, /// <- Causes the IFU to stall (MIPS ISA)
IsNonSpeculative, ///< Should not be executed speculatively
@@ -150,12 +150,12 @@ class StaticInstBase : public RefCounted
//Flags for microcode
IsMacroop, ///< Is a macroop containing microops
IsMicroop, ///< Is a microop
IsDelayedCommit, ///< This microop doesn't commit right away
IsLastMicroop, ///< This microop ends a microop sequence
IsFirstMicroop, ///< This microop begins a microop sequence
IsMicroop, ///< Is a microop
IsDelayedCommit, ///< This microop doesn't commit right away
IsLastMicroop, ///< This microop ends a microop sequence
IsFirstMicroop, ///< This microop begins a microop sequence
//This flag doesn't do anything yet
IsMicroBranch, ///< This microop branches within the microcode for a macroop
IsMicroBranch, ///< This microop branches within the microcode for a macroop
IsDspOp,
NumFlags
@@ -215,26 +215,26 @@ class StaticInstBase : public RefCounted
/// of the individual flags.
//@{
bool isNop() const { return flags[IsNop]; }
bool isNop() const { return flags[IsNop]; }
bool isMemRef() const { return flags[IsMemRef]; }
bool isLoad() const { return flags[IsLoad]; }
bool isStore() const { return flags[IsStore]; }
bool isStoreConditional() const { return flags[IsStoreConditional]; }
bool isMemRef() const { return flags[IsMemRef]; }
bool isLoad() const { return flags[IsLoad]; }
bool isStore() const { return flags[IsStore]; }
bool isStoreConditional() const { return flags[IsStoreConditional]; }
bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
bool isCopy() const { return flags[IsCopy];}
bool isInteger() const { return flags[IsInteger]; }
bool isFloating() const { return flags[IsFloating]; }
bool isInteger() const { return flags[IsInteger]; }
bool isFloating() const { return flags[IsFloating]; }
bool isControl() const { return flags[IsControl]; }
bool isCall() const { return flags[IsCall]; }
bool isReturn() const { return flags[IsReturn]; }
bool isDirectCtrl() const { return flags[IsDirectControl]; }
bool isControl() const { return flags[IsControl]; }
bool isCall() const { return flags[IsCall]; }
bool isReturn() const { return flags[IsReturn]; }
bool isDirectCtrl() const { return flags[IsDirectControl]; }
bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
bool isCondCtrl() const { return flags[IsCondControl]; }
bool isUncondCtrl() const { return flags[IsUncondControl]; }
bool isCondCtrl() const { return flags[IsCondControl]; }
bool isUncondCtrl() const { return flags[IsUncondControl]; }
bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
bool isThreadSync() const { return flags[IsThreadSync]; }
@@ -287,8 +287,8 @@ class StaticInst : public StaticInstBase
typedef TheISA::RegIndex RegIndex;
enum {
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
};