diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index aeebfd6bf5..0ad7283fcd 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -61,6 +61,11 @@ decode QUADRANT default Unknown::unknown() {
                     return std::make_shared<IllegalInstFault>("FPU is off",
                                                                machInst);
 
+                // Mutating any floating point register changes the FS bit
+                // of the STATUS CSR.
+                status.fs = FPUStatus::DIRTY;
+                xc->setMiscReg(MISCREG_STATUS, status);
+
                 Fp2_bits = Mem;
             }}, {{
                 EA = rvZext(Rp1 + offset);
@@ -312,6 +317,11 @@ decode QUADRANT default Unknown::unknown() {
                     return std::make_shared<IllegalInstFault>("FPU is off",
                                                                machInst);
 
+                // Mutating any floating point register changes the FS bit
+                // of the STATUS CSR.
+                status.fs = FPUStatus::DIRTY;
+                xc->setMiscReg(MISCREG_STATUS, status);
+
                 Fc1_bits = Mem;
             }}, {{
                 EA = rvZext(sp + offset);
@@ -495,6 +505,12 @@ decode QUADRANT default Unknown::unknown() {
                     if (status.fs == FPUStatus::OFF)
                         return std::make_shared<IllegalInstFault>(
                                     "FPU is off", machInst);
+
+                    // Mutating any floating point register changes the FS bit
+                    // of the STATUS CSR.
+                    status.fs = FPUStatus::DIRTY;
+                    xc->setMiscReg(MISCREG_STATUS, status);
+
                     freg_t fd;
                     fd = freg(f64(Mem));
                     Fd_bits = fd.v;