From 3a2a917a53f9e95848336a3996256210bdde948a Mon Sep 17 00:00:00 2001 From: Yu-Cheng Chang Date: Sat, 4 May 2024 00:53:43 +0800 Subject: [PATCH] arch-riscv: Fix VCSR read behavoir (#1076) The VCSR should read the value with VXSAT and VXRM
Table 40. vcsr layout
Bits Name Description

XLEN-1:3

Reserved

2:1

vxrm[1:0]

Fixed-point rounding mode

0

vxsat

Fixed-point accrued saturation flag

Change-Id: I1227b920da78026951dfa548e41c8cc56da6caac --- src/arch/riscv/isa.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index 1280a77b87..61b86097f3 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -568,7 +568,7 @@ ISA::readMiscReg(RegIndex idx) } case MISCREG_VCSR: { - return readMiscRegNoEffect(MISCREG_VXSAT) & + return readMiscRegNoEffect(MISCREG_VXSAT) | (readMiscRegNoEffect(MISCREG_VXRM) << 1); } break;