diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index d80c0c7120..84bd81ca0c 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -114,6 +114,7 @@ def operands {{
 
     #Register fields for microops
     'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
+    'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11),
     'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
 
     #General Purpose Floating Point Reg Operands