misc: Replaced master/slave terminology

Change-Id: I4df2557c71e38cc4e3a485b0e590e85eb45de8b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33553
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

src/python/m5/SimObject.py

@@ -186,11 +186,11 @@ def createCxxConfigDirectoryEntryFile(code, name, simobj, is_header):
 
         for port in simobj._ports.values():
             is_vector = isinstance(port, m5.params.VectorPort)
-            is_master = port.role == 'MASTER'
+            is_requestor = port.role == 'GEM5 REQUESTOR'
 
             code('ports["%s"] = new PortDesc("%s", %s, %s);' %
                 (port.name, port.name, cxx_bool(is_vector),
-                cxx_bool(is_master)))
+                cxx_bool(is_requestor)))
 
         code.dedent()
         code('}')

src/python/m5/params.py

@@ -2120,13 +2120,13 @@ class Port(object):
     def cxx_decl(self, code):
         code('unsigned int port_${{self.name}}_connection_count;')
 
-Port.compat('GEM5 REQUESTER', 'GEM5 RESPONDER')
+Port.compat('GEM5 REQUESTOR', 'GEM5 RESPONDER')
 
 class RequestPort(Port):
     # RequestPort("description")
     def __init__(self, desc):
         super(RequestPort, self).__init__(
-                'GEM5 REQUESTER', desc, is_source=True)
+                'GEM5 REQUESTOR', desc, is_source=True)
 
 class ResponsePort(Port):
     # ResponsePort("description")
@@ -2143,7 +2143,7 @@ class VectorRequestPort(VectorPort):
     # VectorRequestPort("description")
     def __init__(self, desc):
         super(VectorRequestPort, self).__init__(
-                'GEM5 REQUESTER', desc, is_source=True)
+                'GEM5 REQUESTOR', desc, is_source=True)
 
 class VectorResponsePort(VectorPort):
     # VectorResponsePort("description")

src/python/m5/util/dot_writer.py

@@ -42,7 +42,7 @@
 # view. The output generated by do_dot() is a DOT-based figure (as a
 # pdf and an editable svg file) and its source dot code. Nodes are
 # components, and edges represent the memory hierarchy: the edges are
-# directed, from a master to slave. Initially all nodes are
+# directed, from a requestor to responder. Initially all nodes are
 # generated, and then all edges are added. do_dot should be called
 # with the top-most SimObject (namely root but not necessarily), the
 # output folder and the output dot source filename. From the given