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misc: Replaced master/slave terminology

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Change-Id: I4df2557c71e38cc4e3a485b0e590e85eb45de8b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33553
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Shivani Parekh
2020-08-24 11:47:44 -07:00
parent 468b343837
commit 392c1ced53
254 changed files with 2690 additions and 2521 deletions
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22
src/cpu/BaseCPU.py
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@@ -182,25 +182,25 @@ class BaseCPU(ClockedObject):
if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
_uncached_slave_ports = []
_uncached_master_ports = []
_uncached_interrupt_response_ports = []
_uncached_interrupt_request_ports = []
if buildEnv['TARGET_ISA'] == 'x86':
_uncached_slave_ports += ["interrupts[0].pio",
"interrupts[0].int_slave"]
_uncached_master_ports += ["interrupts[0].int_master"]
_uncached_interrupt_response_ports += ["interrupts[0].pio",
"interrupts[0].int_responder"]
_uncached_interrupt_request_ports += ["interrupts[0].int_requestor"]
def createInterruptController(self):
self.interrupts = [ArchInterrupts() for i in range(self.numThreads)]
def connectCachedPorts(self, bus):
for p in self._cached_ports:
exec('self.%s = bus.slave' % p)
exec('self.%s = bus.cpu_side_ports' % p)
def connectUncachedPorts(self, bus):
for p in self._uncached_slave_ports:
exec('self.%s = bus.master' % p)
for p in self._uncached_master_ports:
exec('self.%s = bus.slave' % p)
for p in self._uncached_interrupt_response_ports:
exec('self.%s = bus.mem_side_ports' % p)
for p in self._uncached_interrupt_request_ports:
exec('self.%s = bus.cpu_side_ports' % p)
def connectAllPorts(self, cached_bus, uncached_bus = None):
self.connectCachedPorts(cached_bus)
@@ -237,7 +237,7 @@ class BaseCPU(ClockedObject):
self.toL2Bus = xbar if xbar else L2XBar()
self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
self.toL2Bus.master = self.l2cache.cpu_side
self.toL2Bus.mem_side_ports = self.l2cache.cpu_side
self._cached_ports = ['l2cache.mem_side']
def createThreads(self):