configs, mem-ruby: Implement DVMOps in CHI

1) Handling TLBI/TLBI_SYNC requests from the PE in the CHI Request Node
(Generating DVMOps)

2) Adding a new machine type for the Misc Node (MN) that handles DVMOps
from the Request Node (RN), following the protocol specified within
the Amba 5 CHI Architecture Specification [1]

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

[1]: https://developer.arm.com/documentation/ihi0050/latest

Change-Id: I9ac00463ec3080c90bb81af721d88d44047123b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57298
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs/ruby/CHI.py

@@ -79,6 +79,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
     # Node types
     CHI_RNF = chi_defs.CHI_RNF
     CHI_HNF = chi_defs.CHI_HNF
+    CHI_MN = chi_defs.CHI_MN
     CHI_SNF_MainMem = chi_defs.CHI_SNF_MainMem
     CHI_SNF_BootMem = chi_defs.CHI_SNF_BootMem
     CHI_RNI_DMA = chi_defs.CHI_RNI_DMA
@@ -140,6 +141,14 @@ def create_system(options, full_system, system, dma_ports, bootmem,
         network_nodes.append(rnf)
         network_cntrls.extend(rnf.getNetworkSideControllers())
 
+    # Creates one Misc Node
+    ruby_system.mn = [ CHI_MN(ruby_system, [cpu.l1d for cpu in cpus]) ]
+    for mn in ruby_system.mn:
+        all_cntrls.extend(mn.getAllControllers())
+        network_nodes.append(mn)
+        network_cntrls.extend(mn.getNetworkSideControllers())
+        assert(mn.getAllControllers() == mn.getNetworkSideControllers())
+
     # Look for other memories
     other_memories = []
     if bootmem:

configs/ruby/CHI_config.py

@@ -230,6 +230,9 @@ class CHI_L1Controller(CHI_Cache_Controller):
         self.number_of_TBEs = 16
         self.number_of_repl_TBEs = 16
         self.number_of_snoop_TBEs = 4
+        self.number_of_DVM_TBEs = 16
+        self.number_of_DVM_snoop_TBEs = 4
+
         self.unify_repl_TBEs = False
 
 class CHI_L2Controller(CHI_Cache_Controller):
@@ -262,6 +265,8 @@ class CHI_L2Controller(CHI_Cache_Controller):
         self.number_of_TBEs = 32
         self.number_of_repl_TBEs = 32
         self.number_of_snoop_TBEs = 16
+        self.number_of_DVM_TBEs = 1 # should not receive any dvm
+        self.number_of_DVM_snoop_TBEs = 1 # should not receive any dvm
         self.unify_repl_TBEs = False
 
 class CHI_HNFController(CHI_Cache_Controller):
@@ -295,8 +300,41 @@ class CHI_HNFController(CHI_Cache_Controller):
         self.number_of_TBEs = 32
         self.number_of_repl_TBEs = 32
         self.number_of_snoop_TBEs = 1 # should not receive any snoop
+        self.number_of_DVM_TBEs = 1 # should not receive any dvm
+        self.number_of_DVM_snoop_TBEs = 1 # should not receive any dvm
         self.unify_repl_TBEs = False
 
+class CHI_MNController(MiscNode_Controller):
+    '''
+    Default parameters for a Misc Node
+    '''
+
+    def __init__(self, ruby_system, addr_range, l1d_caches,
+                 early_nonsync_comp):
+        super(CHI_MNController, self).__init__(
+            version = Versions.getVersion(MiscNode_Controller),
+            ruby_system = ruby_system,
+            mandatoryQueue = MessageBuffer(),
+            triggerQueue = TriggerMessageBuffer(),
+            retryTriggerQueue = TriggerMessageBuffer(),
+            schedRspTriggerQueue = TriggerMessageBuffer(),
+            reqRdy = TriggerMessageBuffer(),
+            snpRdy = TriggerMessageBuffer(),
+        )
+        # Set somewhat large number since we really a lot on internal
+        # triggers. To limit the controller performance, tweak other
+        # params such as: input port buffer size, cache banks, and output
+        # port latency
+        self.transitions_per_cycle = 1024
+        self.addr_ranges = [addr_range]
+        # 16 total transaction buffer entries, but 1 is reserved for DVMNonSync
+        self.number_of_DVM_TBEs = 16
+        self.number_of_non_sync_TBEs = 1
+        self.early_nonsync_comp = early_nonsync_comp
+
+        # "upstream_destinations" = targets for DVM snoops
+        self.upstream_destinations = l1d_caches
+
 class CHI_DMAController(CHI_Cache_Controller):
     '''
     Default parameters for a DMA controller
@@ -333,6 +371,8 @@ class CHI_DMAController(CHI_Cache_Controller):
         self.number_of_TBEs = 16
         self.number_of_repl_TBEs = 1
         self.number_of_snoop_TBEs = 1 # should not receive any snoop
+        self.number_of_DVM_TBEs = 1 # should not receive any dvm
+        self.number_of_DVM_snoop_TBEs = 1 # should not receive any dvm
         self.unify_repl_TBEs = False
 
 class CPUSequencerWrapper:
@@ -535,6 +575,40 @@ class CHI_HNF(CHI_Node):
         return [self._cntrl]
 
 
+class CHI_MN(CHI_Node):
+    '''
+    Encapsulates a Misc Node controller.
+    '''
+
+    class NoC_Params(CHI_Node.NoC_Params):
+        '''HNFs may also define the 'pairing' parameter to allow pairing'''
+        pairing = None
+
+
+    # The CHI controller can be a child of this object or another if
+    # 'parent' if specified
+    def __init__(self, ruby_system, l1d_caches, early_nonsync_comp=False):
+        super(CHI_MN, self).__init__(ruby_system)
+
+        # MiscNode has internal address range starting at 0
+        addr_range = AddrRange(0, size = "1kB")
+
+        self._cntrl = CHI_MNController(ruby_system, addr_range, l1d_caches,
+                                       early_nonsync_comp)
+
+        self.cntrl = self._cntrl
+
+        self.connectController(self._cntrl)
+
+    def connectController(self, cntrl):
+        CHI_Node.connectController(self, cntrl)
+
+    def getAllControllers(self):
+        return [self._cntrl]
+
+    def getNetworkSideControllers(self):
+        return [self._cntrl]
+
 class CHI_SNF_Base(CHI_Node):
     '''
     Creates CHI node controllers for the memory controllers