From 36d65d297699ab227a3ef996e8a52132a7d3c6ab Mon Sep 17 00:00:00 2001
From: Quentin Forcioli <quentin.forcioli@telecom-paris.fr>
Date: Tue, 7 Sep 2021 11:40:54 +0200
Subject: [PATCH] arch-arm: Fixed EL2S system register trapping.

Prevent a disabled El2S from trapping a system register access from EL1S
This commit is part of series of commit to enable booting OPTEE on gem5.

Change-Id: I0258e15b21dd6a69a3e29e88b753825fad648cfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49987
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/arm/insts/misc64.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 0f301b0130..bee1a413d7 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -419,7 +419,7 @@ MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
         break;
        // Generic Timer
       case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
-        trap_to_hyp = el <= EL1 &&
+        trap_to_hyp = EL2Enabled(tc) && el <= EL1 &&
                       isGenericTimerSystemAccessTrapEL2(misc_reg, tc);
         break;
       case MISCREG_DAIF: