mem: Cycles converted to Ticks in atomic cache accesses
This patch fixes an outstanding issue in the cache timing calculations where an atomic access returned a time in Cycles, but the port forwarded it on as if it was in Ticks. A separate patch will update the regression stats.
This commit is contained in:
16
src/mem/cache/cache_impl.hh
vendored
16
src/mem/cache/cache_impl.hh
vendored
@@ -644,7 +644,7 @@ Cache<TagStore>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
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template<class TagStore>
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Cycles
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Tick
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Cache<TagStore>::recvAtomic(PacketPtr pkt)
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{
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Cycles lat = hitLatency;
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@@ -678,7 +678,7 @@ Cache<TagStore>::recvAtomic(PacketPtr pkt)
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pkt->cmdString(), pkt->getAddr());
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}
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return lat;
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return lat * clockPeriod();
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}
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// should assert here that there are no outstanding MSHRs or
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@@ -763,7 +763,7 @@ Cache<TagStore>::recvAtomic(PacketPtr pkt)
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pkt->makeAtomicResponse();
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}
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return lat;
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return lat * clockPeriod();
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}
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@@ -1510,7 +1510,7 @@ Cache<TagStore>::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
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}
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template<class TagStore>
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Cycles
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Tick
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Cache<TagStore>::recvAtomicSnoop(PacketPtr pkt)
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{
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// Snoops shouldn't happen when bypassing caches
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@@ -1519,12 +1519,12 @@ Cache<TagStore>::recvAtomicSnoop(PacketPtr pkt)
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if (pkt->req->isUncacheable() || pkt->cmd == MemCmd::Writeback) {
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// Can't get a hit on an uncacheable address
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// Revisit this for multi level coherence
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return hitLatency;
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return 0;
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}
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BlkType *blk = tags->findBlock(pkt->getAddr());
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handleSnoop(pkt, blk, false, false, false);
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return hitLatency;
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return hitLatency * clockPeriod();
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}
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@@ -1777,8 +1777,6 @@ template<class TagStore>
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Tick
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Cache<TagStore>::CpuSidePort::recvAtomic(PacketPtr pkt)
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{
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// @todo: Note that this is currently using cycles instead of
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// ticks and will be fixed in a future patch
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return cache->recvAtomic(pkt);
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}
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@@ -1825,8 +1823,6 @@ template<class TagStore>
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Tick
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Cache<TagStore>::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
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{
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// @todo: Note that this is using cycles and not ticks and will be
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// fixed in a future patch
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return cache->recvAtomicSnoop(pkt);
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}
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