From 35d8a9fd2f3b84b58e2ab3bf466b461fe3c2b034 Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Sat, 6 Feb 2021 17:17:00 +0530 Subject: [PATCH] arch-power: Refactor load-store instructions This changes the base classes for load-store instructions and introduces two new classes for DS form instructions which use a shifted signed immediate field as the offset from the base address and for X form instructions which use registers for both the offset and the base address. The formats have also been updated to make use of the new base classes. Change-Id: Ib5d1bb5d7747813e0e5b1e3075489f1a3aa72660 Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40892 Reviewed-by: Boris Shingarov Maintainer: Gabe Black Tested-by: kokoro --- src/arch/power/insts/mem.cc | 2 +- src/arch/power/insts/mem.hh | 37 ++++++++++++++++++++++++++++-- src/arch/power/isa/decoder.isa | 4 +--- src/arch/power/isa/formats/mem.isa | 30 ++++++++++++++++-------- 4 files changed, 57 insertions(+), 16 deletions(-) diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc index 596d78d25f..4c2688c8cd 100644 --- a/src/arch/power/insts/mem.cc +++ b/src/arch/power/insts/mem.cc @@ -63,7 +63,7 @@ MemDispOp::generateDisassembly( } // Print the displacement - ss << ", " << (int32_t)disp; + ss << ", " << d; // Print the address register ss << "("; diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh index de9b46cdbe..e982515cbe 100644 --- a/src/arch/power/insts/mem.hh +++ b/src/arch/power/insts/mem.hh @@ -63,11 +63,12 @@ class MemDispOp : public MemOp { protected: - int16_t disp; + int64_t d; /// Constructor MemDispOp(const char *mnem, MachInst _machInst, OpClass __opClass) - : MemOp(mnem, _machInst, __opClass), disp(machInst.d) + : MemOp(mnem, _machInst, __opClass), + d(sext<16>(machInst.d)) { } @@ -75,6 +76,38 @@ class MemDispOp : public MemOp Addr pc, const Loader::SymbolTable *symtab) const override; }; +/** + * Class for memory operations with shifted displacement. + */ +class MemDispShiftOp : public MemOp +{ + protected: + + int64_t ds; + + /// Constructor + MemDispShiftOp(const char *mnem, MachInst _machInst, OpClass __opClass) + : MemOp(mnem, _machInst, __opClass), + ds(sext<14>(machInst.ds)) + { + } +}; + + +/** + * Class for memory operations with register indexed addressing. + */ +class MemIndexOp : public MemOp +{ + protected: + + /// Constructor + MemIndexOp(const char *mnem, MachInst _machInst, OpClass __opClass) + : MemOp(mnem, _machInst, __opClass) + { + } +}; + } // namespace PowerISA #endif //__ARCH_POWER_INSTS_MEM_HH__ diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index ac52ab33a3..e00ce3be9d 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -527,9 +527,7 @@ decode PO default Unknown::unknown() { 55: StoreDispUpdateOp::stfdu({{ Mem_df = Fs; }}); 58: decode DS_XO { - 2: LoadDispOp::lwa({{ Rt = Mem_sw; }}, - {{ EA = Ra + (disp & 0xfffffffc); }}, - {{ EA = disp & 0xfffffffc; }}); + 2: LoadDispShiftOp::lwa({{ Rt = Mem_sw; }}); } format FloatArithOp { diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa index c7be2b10d9..1b2500c5d9 100644 --- a/src/arch/power/isa/formats/mem.isa +++ b/src/arch/power/isa/formats/mem.isa @@ -240,7 +240,7 @@ def format LoadIndexOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, mem_flags = [], inst_flags = []) {{ (header_output, decoder_output, decode_block, exec_output) = \ GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, - 'MemOp', 'Load', mem_flags, inst_flags) + 'MemIndexOp', 'Load', mem_flags, inst_flags) }}; @@ -249,7 +249,7 @@ def format StoreIndexOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, mem_flags = [], inst_flags = []) {{ (header_output, decoder_output, decode_block, exec_output) = \ GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, - 'MemOp', 'Store', mem_flags, inst_flags) + 'MemIndexOp', 'Store', mem_flags, inst_flags) }}; @@ -262,7 +262,7 @@ def format LoadIndexUpdateOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, # Generate the class (header_output, decoder_output, decode_block, exec_output) = \ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - base_class = 'MemOp', + base_class = 'MemIndexOp', exec_template_base = 'Load') }}; @@ -276,13 +276,13 @@ def format StoreIndexUpdateOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, # Generate the class (header_output, decoder_output, decode_block, exec_output) = \ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - base_class = 'MemOp', + base_class = 'MemIndexOp', exec_template_base = 'Store') }}; -def format LoadDispOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, - ea_code_ra0 = {{ EA = disp; }}, +def format LoadDispOp(memacc_code, ea_code = {{ EA = Ra + d; }}, + ea_code_ra0 = {{ EA = d; }}, mem_flags = [], inst_flags = []) {{ (header_output, decoder_output, decode_block, exec_output) = \ GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, @@ -290,8 +290,8 @@ def format LoadDispOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, }}; -def format StoreDispOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, - ea_code_ra0 = {{ EA = disp; }}, +def format StoreDispOp(memacc_code, ea_code = {{ EA = Ra + d; }}, + ea_code_ra0 = {{ EA = d; }}, mem_flags = [], inst_flags = []) {{ (header_output, decoder_output, decode_block, exec_output) = \ GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, @@ -299,7 +299,17 @@ def format StoreDispOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, }}; -def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, +def format LoadDispShiftOp(memacc_code, + ea_code = {{ EA = Ra + (ds << 2); }}, + ea_code_ra0 = {{ EA = (ds << 2); }}, + mem_flags = [], inst_flags = []) {{ + (header_output, decoder_output, decode_block, exec_output) = \ + GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, + 'MemDispShiftOp', 'Load', mem_flags, inst_flags) +}}; + + +def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + d; }}, mem_flags = [], inst_flags = []) {{ # Add in the update code @@ -313,7 +323,7 @@ def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, }}; -def format StoreDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, +def format StoreDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + d; }}, mem_flags = [], inst_flags = []) {{ # Add in the update code